LTC2360HS6 View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC2360HS6

100ksps/250ksps/500ksps, 12-Bit Serial ADCs in TSOT-23

Linear Technology 

LTC2360/LTC2361/LTC2362

APPLICATIONS INFORMATION

BOARD LAYOUT AND BYPASSING

Wire wrap boards are not recommended for high resolution

and/or high speed A/D converters. To obtain the best per-

formance from the LTC2360/LTC2361/LTC2362, a printed

circuit board with ground plane is required. Layout for the

printed circuit board should ensure that digital and analog

signal lines are separated as much as possible. In particular,

care should be taken not to run any digital track alongside

an analog signal track or underneath the ADC. The analog

input should be screened by the ground plane.

High quality tantalum and ceramic bypass capacitors

should be used at the VDD pin as shown in the Block

Diagram on the first page of this data sheet. For optimum

performance, a 2.2μF surface mount AVX capacitor with

a 0.1μF ceramic is recommended for the VDD and VREF

pins. Alternatively, 2.2μF ceramic chip capacitors such as

Murata GRM235Y5V106Z016 may be used. The capacitors

must be located as close to the pins as possible. The traces

connecting the pins and the bypass capacitors must be

kept short and should be made as wide as possible.

Figure 16 shows the recommended system ground con-

nections. All analog circuitry grounds should be terminated

at the LTC2360/LTC2361/LTC2362. The ground return

from the LTC2360/LTC2361/LTC2362 to the power supply

should be low impedance for noise free operation. Digital

circuitry grounds must be connected to the digital supply

common.

In applications where the ADC data outputs and control sig-

nals are connected to a continuously active microprocessor

bus, it is possible to get errors in the conversion results.

These errors are due to feedthrough from the micropro-

cessor to the successive approximation comparator. The

problem can be eliminated by forcing the microprocessor

into a wait state during conversion or by using three-state

buffers to isolate the ADC data bus.

CVDD

+

2.2μF

PIN 1

VDD

CAIN

GND

AIN

CONV

SDO

SCK

VIAS TO GROUND PLANE

236012 F16

Figure 16. Power Supply Ground Practice

18

236012fa

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