LH28F020SU-N View Datasheet(PDF) - Sharp Electronics
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Description
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LH28F020SU-N Datasheet PDF : 31 Pages
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LH28F020SU-N
2M (256K × 8) Flash Memory
The LH28F020SU-N will be available in a 32-pin, 1.2
mm thick, 8 mm × 20 mm TSOP (Type I) package. This
form factor and pinout allow for very high board layout
densities.
A Command User Interface (CUI) serves as the sys-
tem interface between the microprocessor or
microcontroller and the internal memory operation.
Internal Algorithm Automation allows Byte Writes and
Block Erase operations to be executed using a Two-
Write command sequence to the CUI in the same way
as the LH28F008SA 8M Flash memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
• Software Locking of Memory Blocks
• Memory Protection Set/Reset Capability
• Two-Byte Serial Writes in 8-bit Systems
• Erase All Unlocked Blocks
Writing of memory data is performed typically within
13 µs. A Block Erase operation erases one of the 16
blocks in typically 0.6 seconds, independent of the other
blocks.
LH28F020SU-N allows to erase all unlocked blocks.
It is desirable in case you have to implement Erase
operation maximum 16 times.
LH28F020SU-N enables two-byte serial Write
which is operated by three times command input. This
feature can improve system write performance by up to
typically 10 µs per byte.
All operations are started by a sequence of Write
commands to the device. Status Register (described in
detail later) provide information on the progress of the
requested operation.
Same as the LH28F008SA, LH28F020SU-N
requires an operation to complete before the next
operation can be requested, also it allows to suspend
block erase to read data from any other block, and al-
low to resume erase operation.
The LH28F020SU-N provides user-selectable block
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable OS or
Application Code. Each block has an associated
non-volatile lock-bit which determines the lock status of
the block. In addition, the LH28F020SU-N has a soft-
ware controlled master Write Protect circuit which pre-
vents any modifications to memory blocks whose
lock-bits are set.
When the device power-up, Write Protect Set/
Confirm command must be written. Otherwise, all lock
bits in the device remain being locked, can’t perform
the Write to each block and single Block Erase. Write
Protect Set/Confirm command must be written to
reflect the actual lock status. However, when the device
power-on, Erase All Unlocked Blocks can be used. If
used, Erase is performed with reflecting actual lock sta-
tus, and after that Write and Block Erase can be used.
The LH28F020SU-N contains Status Register to
accomplish various functions:
• A Compatible Status Register (CSR) which is
100% compatible with the LH28F008SA Flash
memory’s Status Register. This register, when used
alone, provides a straightforward upgrade capabil-
ity to the LH28F020SU-N from a LH28F008SA
based design.
The LH28F020SU-N is specified for a maximum
access time of 80 ns (tACC) at 5 V operation (4.5 to
5.5 V) over the commercial temperature range (0 to
+70°C).
The LH28F020SU-N incorporates an Automatic
Power Saving (APS) feature which substantially reduces
the active current when the device is in static mode of
operation (addresses not switching).
In APS mode, the typical ICC current is 2 mA at 5.0 V.
A chip reset mode of operation is enabled when CE »,
WE » and OE » hold low more than 5 µs. In this mode, all
operations are aborted, WSM is reset and CSR regis-
ter is cleared. If CE » and or WE » and or OE » and or goes
high, chip reset mode will be finished. It needs more
than 500 ns from one of the CE », WE » or OE » goes high
until output data are valid.
A CMOS Standby mode of operations is enabled
when CE » transitions high will all input control pins at
CMOS levels. In this mode, the device draws an ICC
standby current of 10 µA.
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