ADSP-BF539F(RevA) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-BF539F Datasheet PDF : 60 Pages
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ADSP-BF539/ADSP-BF539F
PIN DESCRIPTIONS
ADSP-BF539/ADSP-BF539F processor pin definitions are listed
in Table 10.
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins, which are driven high.
If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pull-ups or pull-downs, as noted
in the table.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function-
ality is shown in italics.
Table 10. Pin Descriptions
Pin Name
Memory Interface
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
BR
BG
BGH
Asynchronous Memory Control
AMS3–0
ARDY
AOE
ARE
AWE
Flash Control
FCE
FRESET
Synchronous Memory Control
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
Timers
TMR0
TMR1/PPI_FS1
TMR2/PPI_FS2
Type Description
Driver
Type1
O Address Bus for Async/Sync Access
A
I/O Data Bus for Async/Sync Access
A
O Byte Enables/Data Masks for Async/Sync Access
A
I
Bus Request. (This pin should be pulled high when not used.)
O Bus Grant
A
O Bus Grant Hang
A
O Bank Select
A
I
Hardware Ready Control (This pin should always be pulled low when not used.)
O Output Enable
A
O Read Enable
A
O Write Enable
A
I
Flash Enable (This pin should be left unconnected or pulled low for the
ADSP-BF539.)
I
Flash Reset (This pin should be left unconnected or pulled low for the
ADSP-BF539.)
O Row Address Strobe
A
O Column Address Strobe
A
O Write Enable
A
O Clock Enable
A
O Clock Output
B
O A10 Pin
A
O Bank Select
A
I/O Timer 0
C
I/O Timer 1/PPI Frame Sync1
C
I/O Timer 2/PPI Frame Sync2
C
Rev. A | Page 21 of 60 | February 2008
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