ADSP-21368SKBPZENG View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21368SKBPZENG

SHARC® Processor

Analog Devices 

ADSP-21368

KEY FEATURES – PROCESSOR CORE

At 400 MHz (2.5 ns) core instruction rate, the ADSP-21368

performs 2.4 GFLOPS/800 MMACS

2M bit on-chip SRAM (0.75M Bit in blocks 0 and 1, and 250K

Bit in blocks 2 and 3) for simultaneous access by the core

processor and DMA

6M bit on-chip mask-programmable ROM (3M bit in block 0

and 3M bit in block 1)

Dual Data Address Generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single Instruction Multiple Data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution

Code compatibility with other SHARC family members at

the assembly level

Parallelism in busses and computational units allows: Sin-

gle cycle executions (with or without SIMD) of a multiply

operation, an ALU operation, a dual memory read or

write, and an instruction fetch

Transfers between memory and core at a sustained 6.0G

bytes/s bandwidth at 400 MHz core instruction rate

INPUT/OUTPUT FEATURES

DMA Controller supports:

34 zero-overhead DMA channels for transfers between

ADSP-21368 internal memory and a variety of

peripherals

32-bit DMA transfers at core clock speed, in parallel with

full-speed processor execution

32-Bit Wide External Port Provides Glueless Connection to

both Synchronous (SDRAM) and Asynchronous Memory

Devices

Programmable wait state options: 2 to 31 SCLK cycles

Delay-line DMA engine maintains circular buffers in exter-

nal memory with tap/offset based reads

SDRAM accesses at 166MHz and Asynchronous accesses at

66MHz

Shared-memory support allows multiple DSPs to automat-

ically arbitrate for the bus and gluelessly access a

common memory device

Multiprocessing Support Provides:

Glueless Connection for Scalable DSP Multiprocessing

Architecture

Distributed On-Chip Bus Arbitration for Parallel Bus

Connect of Up to Four ADSP-21368s and Global Memory

4 Memory Select lines allows multiple external memory

devices

Preliminary Technical Data

Digital Audio Interface (DAI) includes eight serial ports, four

Precision Clock Generators, an Input Data Port, an S/PDIF

transceiver, an 8-channel asynchronous sample rate con-

verter, and a Signal Routing Unit

Digital Peripheral Interface (DPI) includes, three timers, two

UARTs, two SPI ports, and a two wire interface port

Outputs of PCG's C and D can be driven on to DPI pins

Eight dual data line serial ports that operate at up to 50M

bits/s on each data line — each has a clock, frame sync and

two data lines that can be configured as either a receiver or

transmitter pair

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony interfaces

such as H.100/H.110

Up to 16 TDM stream support, each with 128 channels per

frame

Companding selection on a per channel basis in TDM mode

Input data port, configurable as eight channels of serial data

or seven channels of serial data and a single channel of up

to a 20-bit wide parallel data

Signal routing unit provides configurable and flexible con-

nections between all DAI/DPI components

2 Muxed Flag/IRQ lines

1 Muxed Flag/Timer expired line /MS pin

1 Muxed Flag/IRQ /MS pin

DEDICATED AUDIO COMPONENTS

S/PDIF Compatible Digital Audio receiver/transmitter sup-

ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards

Left-justified, I2S or right-justified serial data input with

16, 18, 20 or 24-bit word widths (transmitter)

Sample Rate Converter (SRC) contains a Serial Input Port, De-

emphasis Filter, Sample Rate Converter (SRC) and Serial

Output Port providing up to -128db SNR performance.

Supports Left Justified, I2S, TDM and Right Justified 24, 20,

18 and 16-bit serial formats (input)

Pulse Width Modulation provides:

16 PWM outputs configured as four groups of four outputs

supports center-aligned or edge-aligned PWM waveforms

ROM Based Security features include:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Dual voltage: 3.3 V I/O, 1.3 V core

Available in 256-ball BGA Package (see Ordering Guide on

page 46)

Rev. PrA | Page 2 of 48 | November 2004

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