ADSP-21371(Rev0) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21371
(Rev.:Rev0)

SHARC® Processor

Analog Devices 

ADSP-21371

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 5:

A = asynchronous, I = input, O = output, S = synchronous,

(A/D) = active drive, (O/D) = open drain, and T = three-state,

(pd) = pull-down resistor, (pu) = pull-up resistor.

Table 5. Pin List

Name

ADDR23–0

DATA31–0

DAI _P20–1

DPI _P14–1

ACK

RD

WR

SDRAS

SDCAS

SDWE

SDCKE

SDA10

SDCLK

MS0–1

Type

O/T (pu)

I/O (pu)

I/O with

programmable pu1

I/O with

programmable pu1

I (pu)

O/T (pu)

O/T (pu)

O/T (pu)

O/T (pu)

O/T (pu)

O/T (pu)

O/T (pu)

O/T

O/T (pu)

State During

and After Reset

Pulled high/

driven low

Pulled high/

pulled high

Pulled high/

pulled high

Pulled high/

pulled high

Pulled high/

driven high

Pulled high/

driven high

Pulled high/

driven high

Pulled high/

driven high

Pulled high/

driven high

Pulled high/

driven high

Pulled high/

driven low

High-Z/driving

Pulled high/

driven high

Description

External Address. The ADSP-21371 outputs addresses for external memory and periph­

erals on these pins.

ExternalData.The data pins can be multiplexedto support the external memory interface

data (I/O), the PDAP (I), FLAGS (I/O) and PWM (O). After reset, all DATA pins are in EMIF

mode and FLAG(0-3) pins will be in FLAGS mode (default). When configured in the

IDP_PDAP_CTL register, IDP channel 0 scans the DATA31–8 pins for parallel input

data.

Digital Applications Interface Pins. These pins provide the physical interface to the DAI

SRU. The DAI SRU configuration registers define the combination of on-chip audiocentric

peripheral inputs or outputs connected to the pin and to the pin’s output enable. The

configuration registers of these peripherals then determines the exact behavior of the pin.

Any input or output signal present in the DAI SRU may be routed to any of these pins. The

DAI SRU provides the connection from the serial ports, the S/PDIF module, input data ports

(2), and the precision clock generators (4), to the DAI_P20–1 pins. Pullups can be disabled

via the DAI_PIN_PULLUP register.

Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.

The DPI SRU configuration registers define the combination of on-chip peripheral inputs

or outputs connected to the pin and to the pin’s output enable. The configuration registers

of these peripherals then determines the exact behavior of the pin. Any input or output

signal present in the DPI SRU may be routed to any of these pins. The DPI SRU provides the

connection from the timers (2), SPIs (2), UART (1), flags (12), and general-purpose I/O (9) to

the DPI_P14–1 pins. Pull-ups can be disabled via the DPI_PIN_PULLUP register.

Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an

external memory access. ACK is used by I/O devices, memory controllers, or other periph­

erals to hold off completion of an external memory access.

External Port Read Enable. RD is asserted whenever the ADSP-21371 reads a word from

external memory. RD has a 22.5 kΩ internal pull-up resistor.

External Port Write Enable. WR is asserted when the ADSP-21371 writes a word to

external memory. WR has a 22.5 kΩ internal pull-up resistor.

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other

SDRAM command pins, defines the operation for the SDRAM to perform.

SDRAM Column Address Select. Connect to SDRAM's CAS pin. In conjunction with other

SDRAM command pins, defines the operation for the SDRAM to perform.

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.

SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK signal.

For details, see the data sheet supplied with the SDRAM device.

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-

SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.

SDRAM Clock.

Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre­

sponding banks of external memory. The MS3-0 lines are decoded memory address lines

that change at the same time as the other address lines. When no external memory access

is occurring the MS3-0 lines are inactive; they are active however when a conditional

memory access instruction is executed, whether or not the condition is true.

The MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the

ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21367/8/9 Processors.

Rev. 0 | Page 12 of 48 | June 2007

Share Link: