ADSP-21371(Rev0) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21371
(Rev.:Rev0)

SHARC® Processor

Analog Devices 

UART Port

The ADSP-21371 processor provides a full-duplex Universal

Asynchronous Receiver/Transmitter (UART) port, which is

fully compatible with PC-standard UARTs. The UART port

provides a simplified UART interface to other peripherals or

hosts, supporting full-duplex, DMA-supported, asynchronous

transfers of serial data. The UART also has multiprocessor com­

munication capability using 9-bit address detection. This allows

it to be used in multidrop networks through the RS-485 data

interface standard. The UART port also includes support for 5

to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The

UART port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans­

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

The UART port's baud rate, serial data format, error code gen­

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (fPCLK/ 1,048,576) to

(fPCLK/16) bits per second.

• Supporting data formats from 7 to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

Timers

The ADSP-21371 has a total of three timers: a core timer that

can generate periodic software interrupts and two general pur­

pose timers that can generate periodic interrupts and be

independently set to operate in one of three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

The core timer can be configured to use FLAG3 as a timer

expired signal, and each general-purpose timer has one bidirec­

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin­

gle control and status register enables or disables both general-

purpose timers independently.

ADSP-21371

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire, serial bus used to move 8-bit

data while maintaining compliance with the I2C bus protocol.

The TWI master incorporates the following features:

• 7-bit addressing

• Simultaneous master and slave operation on multiple

device systems with support for multi master data

arbitration

• Digital filtering and timed event processing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave­

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period.

This results in PWM patterns that are symmetrical about the

mid-point of the PWM period. In double update mode, a sec­

ond updating of the PWM registers is implemented at the mid­

point of the PWM period. In this mode, it is possible to produce

asymmetrical PWM patterns that produce lower harmonic dis­

tortion in three-phase PWM inverters.

ROM Based Security

The ADSP-21371 has a ROM security feature that provides

hardware support for securing user software code by preventing

unauthorized reading from the internal code when enabled.

When using this feature, the processor does not boot-load any

external code, executing exclusively from internal SRAM/ROM.

Additionally, the processor is not freely accessible via the JTAG

port. Instead, a unique 64-bit key, which must be scanned in

through the JTAG or Test Access Port will be assigned to each

customer. The device will ignore a wrong key. Emulation fea­

tures and external boot modes are only available after the

correct key is scanned.

Rev. 0 | Page 9 of 48 | June 2007

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