ADSP-21371BSWZ-2B(RevD) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21371BSWZ-2B
(Rev.:RevD)

SHARC Processor

Analog Devices 

ADSP-21371/ADSP-21375

SHARC FAMILY CORE ARCHITECTURE

The ADSP-21371/ADSP-21375 processors are code compatible

at the assembly level with the ADSP-2136x, ADSP-2126x,

ADSP-21160x, and ADSP-21161N, and with the first generation

ADSP-2106x SHARC processors. The ADSP-21371/

ADSP-21375 processors share architectural features with the

ADSP-2126x, ADSP-2136x, and ADSP-2116x SIMD SHARC

processors, as shown in Figure 2 and detailed in the following

sections.

SIMD Computational Engine

The processors contain two computational processing elements

that operate as a single-instruction, multiple-data (SIMD)

engine. The processing elements are referred to as PEX and

PEY, and each contains an ALU, multiplier, shifter, and register

file. PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. When this mode is

enabled, the same instruction is executed in both processing ele-

ments, but each processing element operates on different data.

This architecture is efficient at executing math intensive DSP

algorithms.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

S

SIMD Core

DMD/PMD 64

DAG1

16x32

DAG2

16x32

JTAG FLAG TIMER INTERRUPT CACHE

5 STAGE

PROGRAM SEQUENCER

PM ADDRESS 24

PM DATA 48

PM ADDRESS 32

DM ADDRESS 32

PM DATA 64

DM DATA 64

SYSTEM

I/F

USTAT

4x32-BIT

PX

64-BIT

MULTIPLIER SHIFTER ALU

RF

Rx/Fx

PEx

16x40-BIT

DATA

SWAP

RF

Sx/SFx

PEy

16x40-BIT

ALU

SHIFTER MULTIPLIER

MRF

80-BIT

MRB

80-BIT

ASTATx

STYKx

ASTATy

STYKy

MSB

80-BIT

MSF

80-BIT

Figure 2. SHARC Core Block Diagram

Rev. D | Page 4 of 56 | April 2013

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