ADSP-21371KSWZ-2A View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21371KSWZ-2A

SHARC Processor

Analog Devices 

ADSP-21371/ADSP-21375

TABLE OF CONTENTS

Summary ............................................................... 1

Dedicated Audio Components .................................... 1

Revision History ...................................................... 2

General Description ................................................. 3

SHARC Family Core Architecture ............................ 4

Family Peripheral Architecture ................................ 6

I/O Processor Features ......................................... 10

System Design .................................................... 11

Development Tools ............................................. 11

Additional Information ........................................ 12

Pin Function Descriptions ....................................... 13

ADSP-21371/ADSP-21375 Specifications .................... 16

Operating Conditions .......................................... 16

Electrical Characteristics ....................................... 16

Package Information ........................................... 17

REVISION HISTORY

9/09—Rev. B to Rev. C

Corrected all outstanding document errata. Also replaced core

clock references (CCLK) in the timing specifications with

peripheral clock references (PCLK).

Added operating conditions and electrical characteristics

for the 1.0 V, 200 MHz parts.

For this revision the following sections have been removed. For

information see the ADSP-2137x SHARC Processor Hardware

Reference: “Address Data Pins as Flags”, “Address/Data Modes”,

Core Instruction Rate to CLKIN Ratio Modes.”

Revised Figure 1, Functional Block Diagram ....................1

Added Table 2, ADSP-21371/ADSP-21375 Features ..........3

Added Figure 2, SHARC Core Block Diagram ..................4

Added Context Switch ...............................................5

Added Universal Registers ..........................................5

Added Timer ...........................................................5

Maximum Power Dissipation ................................. 17

Absolute Maximum Ratings ................................... 17

ESD Sensitivity ................................................... 17

Timing Specifications ........................................... 17

Output Drive Currents ......................................... 45

Test Conditions .................................................. 45

Capacitive Loading .............................................. 45

Thermal Characteristics ........................................ 46

208-Lead LQFP_EP Pinout ....................................... 47

Package Dimensions ............................................... 51

Automotive Products .............................................. 52

Ordering Guide ..................................................... 52

Added On-Chip Memory Bandwidth ............................ 5

Added External Port Throughput ................................. 8

Added Input Data Port (IDP) ...................................... 9

Added Precision Clock Generator (PCG) ....................... 9

Added Scatter/Gather DMA .......................................11

Clarified VCO operations in

Voltage Controlled Oscillator .....................................18

Corrected the pins names for the DAI and DPI in 208-Lead

LQFP_EP Pinout .....................................................47

Added Automotive Products ......................................52

Rev. C | Page 2 of 52 | September 2009

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