ADSP-21371BSWZ-2B View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-21371BSWZ-2B Datasheet PDF : 52 Pages
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GENERAL DESCRIPTION
The ADSP-21371/ADSP-21375 SHARC® processors are mem-
bers of the SIMD SHARC family of DSPs that feature Analog
Devices’ Super Harvard Architecture. The processors are source
code compatible with the ADSP-2126x, ADSP-2136x, and
ADSP-2116x DSPs, as well as with first generation ADSP-2106x
SHARC processors in SISD (single-instruction, single-data)
mode. The processors are 32-bit/40-bit floating-point proces-
sors optimized for high performance automotive audio
applications with their large on-chip SRAM and mask-pro-
grammable ROM, multiple internal buses to eliminate I/O
bottlenecks, and an innovative digital applications interface
(DAI).
As shown in the functional block diagram on Page 1, the pro-
cessors use two computational units to deliver a significant
performance increase over the previous SHARC processors on a
range of DSP algorithms. Fabricated in a state-of-the-art, high
speed, CMOS process, the processors achieve an instruction
cycle time of 3.75 ns at 266 MHz. With its SIMD computational
hardware, the processors can perform 1.596 GFLOPS running
at 266 MHz.
Table 1 shows performance benchmarks for these devices.
Table 2 shows the features of the individual product offerings.
Table 1. Processor Benchmarks (at 266 MHz)
Benchmark Algorithm
Speed
(at 266 MHz)
1024 Point Complex FFT (Radix 4, With Reversal) 34.5 μs
FIR Filter (per Tap)1
1.88 ns
IIR Filter (per Biquad)1
7.5 ns
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
16.91 ns
30.07 ns
Divide (y/x)
13.1 ns
Inverse Square Root
20.4 ns
1 Assumes two files in multichannel SIMD mode
Table 2. ADSP-21371/ADSP-21375 Features
Feature
ADSP-21371
Frequency
266 MHz
(3.75 ns)
RAM
1M bit
ROM
4M bits
Pulse-Width
Yes
Modulation
Serial Ports
8
UART
1
Digital Application Yes
Interface (DAI)
ADSP-21375
266 MHz
(3.75 ns)
0.5M bit
2M bits
No
4
1
Yes
ADSP-21371/ADSP-21375
Table 2. ADSP-21371/ADSP-21375 Features (Continued)
Feature
Digital Peripheral
Interface (DPI)
S/PDIF Transceiver
SPI
TWI
Package
ADSP-21371
Yes
Yes
2
Yes
208-Lead LQFP_EP
ADSP-21375
Yes
No
2
Yes
208-Lead LQFP_EP
The diagram on Page 1 shows the two clock domains that make
up the ADSP-2137x processors. The core clock domain contains
the following features:
• Two processing elements, each of which comprises an
ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
• One periodic interval timer with pinout
• On-chip SRAM (1M bit, ADSP-21371; 0.5M bit,
ADSP-21375)
• On-chip mask-programmable ROM (4M bit, ADSP-21371;
2M bit, ADSP-21375)
• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user break-
points which allow flexible exception handling.
The diagram on Page 1 also shows the peripheral clock domains
(also known as the I/O processor) and contains the following
features:
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers
• Peripheral and external port bus for core connection
• Digital applications interface that includes four precision
clock generators (PCG), an S/PDIF-compatible digital
audio receiver/transmitter, an input data port (IDP), eight
serial ports, eight serial interfaces, a 20-bit parallel input
port (PDAP), and a flexible signal routing unit (DAI SRU).
• Digital peripheral interface that includes two timers, one
UART, two serial peripheral interfaces (SPI), a 2-wire
interface (TWI), and a flexible signal routing unit
(DPI SRU).
• External port with AMI and SDRAM controller
• Four units for PWM control
• One MTM for internal to internal memory transfers
Rev. C | Page 3 of 52 | September 2009
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