ADSP-21371KSWZ-2A View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21371KSWZ-2A

SHARC Processor

Analog Devices 

ADSP-21371/ADSP-21375

SDRAM Controller

The SDRAM controller provides an interface to up to four sepa-

rate banks of industry-standard SDRAM devices or DIMMs.

Fully compliant with the SDRAM standard, each bank has its

own memory select line (MS0–MS3), and can be configured to

contain between 16M bytes and 256M bytes of memory.

SDRAM external memory address space is shown in Table 5.

The controller maintains all of the banks as a contiguous

address space so that the processor sees this as a single address

space, even if different size devices are used in the

different banks.

A set of programmable timing parameters is available to config-

ure the SDRAM banks to support slower memory devices. The

memory banks can be configured as 16 bits wide or as

32 bits wide. The SDRAM controller address, data, clock, and

command pins can drive loads up to 30 pF. For larger memory

systems, the SDRAM controller external buffer timing should

be selected and external buffering should be provided so that the

load on the SDRAM controller pins does not exceed 30 pF.

Table 5. External Memory for SDRAM Addresses

Bank

Bank 0

Bank 1

Bank 2

Bank 3

Size in Words

62M

64M

64M

64M

Address Range

0x0020 0000–0x03FF FFFF

0x0400 0000–0x07FF FFFF

0x0800 0000–0x0BFF FFFF

0x0C00 0000–0x0FFF FFFF

Note that the external memory bank addresses shown in Table 5

are for normal word accesses. If 48-bit instructions are placed in

any such bank (with two instructions packed into three 32-bit

locations), then care must be taken to map data buffers in the

same bank. For example, if 2k instructions are placed starting at

the bank 0 base address (0x0020 0000), then the data buffers can

be placed starting at an address that is offset by 3k words

(0x0020 0C00).

External Memory Code Execution

The program sequencer can execute code directly from external

memory bank 0 (SRAM, SDRAM) over the 48-bit external port

data bus (EPD). This allows a reduction in internal memory

size, thereby reducing the die area. With external execution,

programs run at slower speeds since 48-bit instructions are

fetched in parts from a 16-bit external bus coupled with the

inherent latency of fetching instructions from SDRAM. Fetch-

ing instructions from external memory generally takes 1.5

peripheral clock cycles per instruction. Non SDRAM external

memory address space is shown in Table 6.

Table 6. External Memory for Non SDRAM Addresses

Bank

Bank 0

Bank 1

Bank 2

Bank 3

Size in Words

14M

16M

16M

16M

Address Range

0x0020 0000–0x00FF FFFF

0x0400 0000–0x04FF FFFF

0x0800 0000–0x08FF FFFF

0x0C00 0000–0x0CFF FFFF

External Port Throughput

The throughput for the external port, based on 133 MHz clock

and 32-bit data bus, is 177M bytes/s for the AMI and 532M

bytes/s for SDRAM.

Asynchronous Memory Controller

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, ROM, flash, and EPROM,

as well as I/O devices that interface with standard memory con-

trol lines. Bank 0 occupies a 14.7M word window and banks 1, 2,

and 3 occupy a 16M word window in the processor’s address

space but, if not fully populated, these windows are not made

contiguous by the memory controller logic. The banks can also

be configured as 8-bit or 16-bit wide buses for ease of interfac-

ing to a range of memories and I/O devices tailored either to

high performance or to low cost and power.

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period.

This results in PWM patterns that are symmetrical about the

mid-point of the PWM period. In double update mode, a sec-

ond updating of the PWM registers is implemented at the mid-

point of the PWM period. In this mode, it is possible to produce

asymmetrical PWM patterns that produce lower harmonic dis-

tortion in three-phase PWM inverters.

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to

connect various peripherals to any of the processor’s DAI pins

(DAI_P1 to DAI_P20).

Programs make these connections using the signal routing unit

(SRU), shown in Figure 1.

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

Rev. C | Page 8 of 52 | September 2009

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