ADSP-BF538 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF538

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF538/ADSP-BF538F

In addition to the three general-purpose programmable timers,

a fourth timer is also provided. This extra timer is clocked by the

internal processor clock and is typically used as a system tick

clock for generation of operating system periodic interrupts.

SERIAL PORTS (SPORTs)

The ADSP-BF538/ADSP-BF538F processors incorporate four

dual-channel synchronous serial ports for serial and multipro-

cessor communications. The SPORTs support the following

features:

• I2S capable operation.

• Bidirectional operation – Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels

of I2S stereo audio.

• Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

• Clocking – Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.

• Word length – Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most significant bit

first or least significant bit first.

• Framing – Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulsewidths and early or late

frame sync.

• Companding in hardware – Each SPORT can perform

A-law or μ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without additional

latencies.

• DMA operations with single-cycle overhead – Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer or buffers through

DMA.

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1024 channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORTS

The ADSP-BF538/ADSP-BF538F processors incorporate three

SPI compatible ports that enable the processor to communicate

with multiple SPI compatible devices.

The SPI interface uses three pins for transferring data: two data

pins (master output-slave input, MOSIx, and master input-slave

output, MISOx) and a clock pin (serial clock, SCKx). An SPI

chip select input pin (SPIxSS) lets other SPI devices select the

Preliminary Technical Data

processor. For SPI0, seven SPI chip select output pins

(SPI0SEL7–1) let the processor select other SPI devices. The SPI

select pins are reconfigured GPIO pins. SPI1 and SPI2 have a

single SPI select for SPI point-to-point communication. Using

these pins, the SPI ports provide a full-duplex, synchronous

serial interface, which supports both master/slave modes and

multimaster environments.

The SPI ports’ baud rate and clock phase/polarities are pro-

grammable, and it has an integrated DMA controller,

configurable to support transmit or receive data streams. Each

SPI’s DMA controller can only service unidirectional accesses at

any given time.

The SPI port’s clock rate is calculated as:

SPI Clock Rate

=

-------------f--S---C---L---K--------------

2 × SPIx_BAUD

Where the 16-bit SPIx_BAUD register contains a value of 2 to

65,535.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

TWO WIRE INTERFACE

The ADSP-BF538/ADSP-BF538F processors have 2 two wire

interface (TWI) modules that are compatible with the Philips

Inter-IC bus standard. The TWI modules offer the capabilities

of simultaneous master and slave operation, support for 7-bit

addressing and multimedia data arbitration. The TWI also

includes master clock synchronization and support for clock

low extension.

The TWI interface uses two pins for transferring clock (SCLx)

and data (SDAx) and supports the protocol at speeds up to

400 kbits/sec.

The TWI interface pins are compatible with 5V logic levels.

UART PORTs

The ADSP-BF538/ADSP-BF538F processors incorporate three

full-duplex Universal Asynchronous Receiver/Transmitter

(UART) ports, which are fully compatible with PC standard

UARTs. The UART ports provide a simplified UART interface

to other peripherals or hosts, supporting full-duplex, DMA sup-

ported, asynchronous transfers of serial data. The UART ports

include support for 5 to 8 data bits, 1 or 2 stop bits, and none,

even, or odd parity. The UART ports support two modes of

operation:

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O mapped UART registers.

The data is double buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. Each UART has two dedicated

Rev. PrD | Page 10 of 56 | May 2006

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