AT89LP4052(2008) View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT89LP4052 Datasheet PDF : 93 Pages
| |||
A second pull-up, called the “weak” pull-up, is turned on when the port register for the pin con-
tains a logic “1” and the pin itself is also at a logic “1” level. This pull-up provides the primary
source current for a quasi-bidirectional pin that is outputting a 1. If this pin is pulled low by an
external device, this weak pull-up turns off, and only the very weak pull-up remains on. In order
to pull the pin low under these conditions, the external device has to sink enough current to over-
power the weak pull-up and pull the port pin below its input threshold voltage.
The third pull-up is referred to as the “strong” pull-up. This pull-up is used to speed up low-to-
high transitions on a quasi-bidirectional port pin when the port register changes from a logic “0”
to a logic “1”. When this occurs, the strong pull-up turns on for one CPU clock, quickly pulling the
port pin high.
When in quasi-bidirectional mode the port pin will always output a “0” when corresponding bit in
the port register is also “0”. When the port register is “1” the pin may be used either as an input
or an output of “1”. The quasi-bidirectional port configuration is shown in Figure 15-1. The input
circuitry of P3.2 and P3.3 is not disabled during Power-down (see Figure 15-3).
Figure 15-1. Quasi-bidirectional Output
VCC
VCC
VCC
From Port
Register
1 Clock Delay
(D Flip-Flop)
Strong
Very
Weak
Weak
Port
Pin
Input
Data
PWD
15.2
Input-only Mode
The input port configuration is shown in Figure 15-2. It is a Schmitt-triggered input for improved
input noise rejection.
Figure 15-2. Input Only
Input
Port
Data
Pin
PWD
Figure 15-3. Input Only for P3.2 and P3.3
Input
Port
Data
Pin
20 AT89LP2052/LP4052
3547I–MICRO–6/08
Share Link: 