DSA400 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSA400

Configurable Four Output, Low Jitter Clock Generator for Automotive

Microchip Technology 

DSA400

4.3 HCSL

33Ω

33Ω

FIGURE 4-3:

Typical HCSL Termination Scheme.

The 33Ω series resistors are needed to avoid excessive ringing.

TABLE 4-3: HCSL OUTPUTS

Parameter Symbol

Min.

Typ.

Max.

Units

Condition

Output Logic

Levels

VOH

0.725

—

VOL

—

—

—

0.1

V Output Logic High, RL = 50Ω

Output Logic Low, RL = 50Ω

Peak-to-Peak

Output Swing

—

—

750

—

mV Single-Ended

Output

tR

Transition Time

(Note 1)

tF

200

—

400

Rise Time, 20% to 80%, RL= 50Ω,

ps CL= 2 pF

200

—

400

Fall Time, 20% to 80%, RL= 50Ω,

CL= 2 pF

Frequency

f0

2.3

—

460

MHz Single Frequency

Output Duty

Cycle

SYM

48

—

52

% Differential

IO Supply

Current (Note 2)

IDDIO

—

20

22

mA Per Output at 125 MHz.

Period Jitter

JPER

—

2.5

—

psRMS

Integrated

Phase Noise

JPH

—

0.25

—

—

0.37

—

psRMS

—

1.7

2.0

Note 1: See the Output Waveform section for more information.

—

200 kHz to 20 MHz @ 156.25 MHz

100 kHz to 20 MHz @ 156.25 MHz

12 kHz to 20 MHz @156.25 MHz

2: The addition of IDDCORE and IDDIO provides the total current consumption of the device.

DS20006356A-page 8

 2020 Microchip Technology Inc.

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