PMS133-H20 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

PMS133-H20

8bit OTP MCU with 12-bit ADC

Unspecified 

PMS133/PMS134

8bit OTP MCU with 12-bit ADC

1. Features

1.1. Special Features

 General purpose series

 Not supposed to use in AC RC step-down powered or high EFT requirement applications.

PADAUK assumes no liability if such kind of applications can not pass the safety regulation tests.

 Operating temperature range: -20°C ~ 70°C

1.2. System Features

Series OTP program memory

PMS133

PMS134

3KW

4KW

RAM

(byte)

256

256

Max IO no.

18

22

Max ADC

Channel no.

14

14

 One hardware 16-bit timer

 Two hardware 8-bit timers with PWM generation

 Three hardware 11-bit PWM generators (PWMG0, PWMG1 & PWMG2)

 One hardware comparator

 Band-gap circuit to provide 1.20V reference voltage

 Up to 14-channel 12-bit resolution ADC with one channel comes from internal band-gap reference voltage

or 0.25*VDD

 ADC reference high voltage: external input, internal VDD, Band-gap 1.20V, 4V, 3V, 2V

 One 1T 8x8 hardware multiplier

 Max. 22 IO pins with optional pull-high resistor

 Three different IO Driving capability group to meet different application requirements

(1) PB4, PB7 Drive/ Sink Current= 30mA/35mA (Strong) and 13mA/17mA (Normal)

(2) Other IOs (except PA5) Drive/ Sink Current = 10mA/(13 or 20) mA

(3) PA5 Sink Current = 10mA

 Every IO pin can be configured to enable wake-up function

 Built-in VDD/2 LCD bias voltage generator to provide maximum 4x10 dots LCD display

 Clock sources: IHRC, ILRC and EOSC (XTAL)

 For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast

 Eight levels of LVR reset ~ 4.0V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V, 1.8V

 Two selectable external interrupt pins by code option

1.3. CPU Features

 8bit high performance RISC CPU

 93 powerful instructions

 Most instructions are 1T execution cycle

 Programmable stack pointer to provide adjustable stack level

 Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer

of Indirect addressing mode

 IO space and memory space are independent

©Copyright 2018, PADAUK Technology Co. Ltd

Page 10 of 106 PDK-DS-PMS133/134-EN_V103 – Nov. 13, 2018

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