1EDF5673K(2019) View Datasheet(PDF) - Infineon Technologies
Part Name
Description
Manufacturer
1EDF5673K Datasheet PDF : 37 Pages
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1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Pin configuration and description
1
Pin configuration and description
PWM 1
DSO-16
16 VDDS
N.C. 2
15 OUTS
VDDI 3 narrow-body 14 GNDS
(150 mil)
GNDI 4 1EDF5673F 13 N.C.
DISABLE 5 wide-body 12 N.C.
(300 mil)
TNEG 6 1EDS5663H 11 VDDG
N.C. 7
10 OUTG
SLDO 8
9 GNDG
GNDI 1
PWM 2
N.C. 3
SLDO 4
DISABLE 5
TNEG 6
VDDI 7
LGA-13 (5 x 5 mm)
13 VDDS
12 OUTS
11 GNDS
1EDF5673K
10 VDDG
9 OUTG
8 GNDG
Figure 1 Pin configuration for DSO-16 and LGA-13 packages, top view
Table 2 Pin description
Pin DSO Pin LGA Symbol Description
1
2
PWM Input signal (default state Low)
Controls switching sequence at OUTG and OUTS
2
3
N.C. Do not connect
3
7
VDDI Input supply voltage (+3.3 V)
4
1
GNDI Input GND
5
5
DISABLE Input signal (defaut state Low)
Logic High is equivalent to a low state at PWM input
6
6
TNEG Resistor programmable input to control the duration t1 of negative "off" level
(Figure 4); t1 = Rt1 * 1.8 pF
7
7
N.C. Not connected
8
4
SLDO N.C. or connected to VDDI: applied voltage (3.3 V) directly used as input supply
voltage
Connected to GNDI: Internal shunt regulator activated (VDD > 3.5 V)
9
8
GNDG Ground for OUTG
10
9
OUTG Output connectd to GaN gate
11
10
VDDG Positive supply voltage for gate connected output stage
12
-
N.C. Not connected
13
-
N.C. Not connected
14
11
GNDS Ground for OUTS (has to be connected with GNDG)
15
12
OUTS Output connected to GaN source
16
13
VDDS Positive supply voltage for source connected output stage (has to be connected
with VDDG)
Final datasheet
4
Rev. 2.10
2019-02-11
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