M185B1-L02 View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
M185B1-L02 Datasheet PDF : 25 Pages
| |||
Doc No.:
Issued Date: Jun. 04, 2008
Model No.: M185B1-L02
Tentative
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
Item
Symbol Min.
Typ. Max. Unit
Note
Frequency
Fc
50.0
76
95 MHz
-
LVDS Clock
Period
High Time
Low Time
LVDS Data
Setup Time
Hold Time
Frame Rate
.tw Vertical Active Display Term
Total
Display
Blank
Total
Horizontal Active Display Term Display
Blank
Tc
10.5 13.2
20
ns
Tch
-
4/7
-
Tc
-
Tcl
-
3/7
-
Tc
-
Tlvs 600
-
-
ps
-
Tlvh 600
-
-
ps
-
Fr
40
60
75
Hz Tv=Tvd+Tvb
Tv
778
806
888
Th
-
Tvd
768
768
768
Th
-
Tvb Tv-Tvd 38 Tv-Tvd Th
-
Th 1446 1560 1936 Tc Th=Thd+Thb
Thd 1366 1366 1366 Tc
-
Thb Th-Thd 194 Th-Thd Tc
-
Note: Because this module is operated by DE only mode, Hsync and Vsync input signals should be set
m to low logic level or ground. Otherwise, this module would operate abnormally.
d.co DE
slc DCLK
.y DE
wwwDATA
INPUT SIGNAL TIMING DIAGRAM
Tv
TVd
TVb
TC
Thb
Th
Thd
15 / 25
Version 0.0
Share Link: 