Issued Date: Jan. 06, 2009
Model No.: M220Z1-L10
Approval
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
LVDS Clock
LVDS Data
Vertical Active Display Term
Horizontal Active Display Term
Item
Frequency
Period
High Time
Low Time
Setup Time
Hold Time
Frame Rate
Total
Display
Blank
Total
Display
Blank
Symbol
Fc
Tc
Tch
Tcl
Tlvs
Tlvh
Fr
Tv
Tvd
Tvb
Th
Thd
Thb
Min.
50
13.4
-
-
600
600
50
1060
1050
Tv-Tvd
890
840
Th-Thd
Typ.
59.5
16.8
4/7
3/7
-
-
60
1080
1050
30
920
840
80
Max.
82
-
-
-
-
-
76
1195
1050
Tv-Tvd
1000
840
Th-Thd
Unit
MHz
ns
Tc
Tc
ps
ps
Hz
Th
Th
Th
Tc
Tc
Tc
Note
-
-
-
-
-
Tv=Tvd+Tvb
-
-
-
Th=Thd+Thb
-
-
Note:(1) Because this module is operated by DE only mode, Hsync and Vsync input signals should be
set to low logic level or ground. Otherwise, this module would operate abnormally.
INPUT SIGNAL TIMING DIAGRAM
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Version 2.0