MCP1812A View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

MCP1812A

Ultra-Low Quiescent Current LDO Regulator for Long-Life Battery-Powered Applications

Microchip Technology 

MCP1811A/11B/12A/12B

4.0 DEVICE OVERVIEW

The MCP1811X/12X family is a 150 mA/300 mA output

current, Low-Dropout (LDO) voltage regulator. The

Low-Dropout voltage of 400 mV, typical, at 300 mA of

current, makes it recommended for long-life

battery-powered applications. The input voltage ranges

from a minimum of 1.8V to 5.5V. The MCP1811X/12X

family features a shutdown control input pin and is

available in nine standard fixed output voltage options:

1V, 1.2V, 1.8V, 2.0V, 2.5V, 2.8V, 3.0V, 3.3V and 4.0V. It

uses a proprietary voltage reference and sensing

scheme to maintain the ultra-low 250 nA quiescent

current.

4.1 Output Capabilities and Current

Limiting

The MCP1811X/12X LDO is tested and ensured to

supply a minimum of 150 mA of output current for

MCP1811X and 300 mA of output current for

MCP1812X.

The MCP1811X/12X devices do not incorporate an

internal voltage divider. This is another design key of

achieving ultra-low power consumption. In addition,

there is a pull-down switch on the output to limit the

overshoot in case of powering an ultra-light load. Due

to the increased leakage through the power transistor

at elevated temperature (> 60°C), the output voltage

can be drifted up (to approximately 210 mV) when the

input supply to the output differential is larger than 3V.

It is recommended to add a very small dummy load

(25 nA, typical) to compensate for the leakage. In

conditions other than mentioned above, the device

does not require a minimum load to regulate the output

voltage within the specified tolerance.

The MCP1811X/12X family also incorporates an output

current foldback protection during overload conditions.

The MCP1811X/12X devices enter foldback when

VOUT falls below 0.6V (typical).

4.2 Output Capacitor

The MCP1811X/12X devices require a minimum output

capacitance of 1 μF (2.2 μF for MCP1812X) for output

voltage stability. Ceramic capacitors are recommended

because of their size, cost and robust environmental

qualities.

The output capacitor should be located as close to the

LDO output as is practical. Ceramic materials, X7R and

X5R, have low-temperature coefficients, and are well

within the acceptable ESR range required. A typical

1 μF X7R 0805 capacitor has an ESR of 20 m.

4.3 Input Capacitor

Low input source impedance is necessary for the LDO

output to operate properly. When operating from

batteries, or in applications with long lead length

(> 10 inches) between the input source and the LDO,

some input capacitance is recommended. A minimum

of 1 μF (2.2 μF for MCP1812X) to 10 μF of capacitance

is recommended for most applications.

For applications that have output step load

requirements, the input capacitance of the LDO is very

important. The input capacitance must provide a

low-impedance source. This allows the LDO to respond

quickly to the output load step. For good step response

performance, the input capacitor should be equivalent

to, or of higher value than, the output capacitor. The

capacitor should be placed as close to the input of the

LDO as is practical. Larger input capacitors will also

help reduce any high-frequency noise on the input and

output of the LDO, as well as the effects of any

inductance that exists between the input source

voltage and the input capacitance of the LDO.

4.4 Shutdown Input (SHDN)

The SHDN input is an active-low input signal that turns

the LDO on and off. The SHDN threshold is a

percentage of the input voltage. The maximum input

low logic level is 20% of VIN and the minimum high logic

level is 70% of VIN.

The SHDN pin ignores low going pulses that are up to

400 ns. This small bit of filtering helps to reject any

system noise spikes on the SHDN input signal.

On the rising edge of the SHDN input, the shutdown

circuitry has a typical 400 μs delay before allowing the

regulator output to turn on. This delay helps to reject

any false turn-on signals or noise on the SHDN input

signal. After the typical 400 μs delay, the regulator

starts charging the load capacitor as the output rises

from 0V to its final regulated value. The charging

current will be limited by the short-circuit current value

of the device. If the SHDN input signal is pulled low

during the typical 400 μs delay period, the timer will be

reset and the delay time will start over again on the next

rising edge of the SHDN input. The total time from the

SHDN input going high (turn-on) to the output being in

regulation shall typically be 400 μs delay time plus

output voltage rise time, which is VR-dependent and

may vary from 200 μs up to 1000 μs for a CLOAD = 1.0 μF

and for a CLOAD = 2.2 μF. Figure 4-1 shows a timing

diagram of the SHDN input.

 2018-2019 Microchip Technology Inc.

DS20006088B-page 20

Share Link: