CLRC63201T0FE View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

CLRC63201T0FE

Standard multi-protocol reader solution

NXP Semiconductors. 

NXP Semiconductors

CLRC632

Standard multi-protocol reader solution

Table 3. Pin description …continued

Pin

Symbol

Type[1] Description

11[3]

NRD

I

not read input generates the strobe signal for reading data from the CLRC632

registers when applied to pins D0 to D7

NDS

I

not data strobe input generates the strobe signal for the read and write cycles

nDStrb

I

not data strobe input generates the strobe signal for the read and write cycles

12

DVSS

G

digital ground

13

D0

O

SPI master in, slave out output

13 to 20[3] D0 to D7

I/O

8-bit bidirectional data bus input/output on pins D0 to D7

AD0 to AD7 I/O

8-bit bidirectional address and data bus input/output on pins AD0 to AD7

21[3]

ALE

I

address latch enable input for pins AD0 to AD5; HIGH latches the internal address

AS

I

address strobe input for pins AD0 to AD5; HIGH latches the internal address

nAStrb

I

not address strobe input for pins AD0 to AD5; LOW latches the internal address

NSS

I

not slave select strobe input for SPI communication

22[3]

A0

I

address line 0 is the address register bit 0 input

nWait

O

not wait output:

LOW starts an access cycle

HIGH ends an access cycle

MOSI

I

SPI master out, slave in

23

A1

I

address line 1 is the address register bit 1 input

24[3]

A2

I

address line 2 is the address register bit 2 input

SCK

I

SPI serial clock input

25

DVDD

P

digital power supply

26

AVDD

P

analog power supply for pins OSCIN, OSCOUT, RX, VMID and AUX

27

AUX

O

auxiliary output is used to generate analog test signals. The output signal is

selected using the TestAnaSelect register’s TestAnaOutSel[4:0] bits

28

AVSS

G

analog ground

29

RX

I

receiver input is used as the card response input. The carrier is load modulated at

13.56 MHz, drawn from the antenna circuit

30

VMID

P

internal reference voltage pin provides the internal reference voltage as a supply

Remark: It must be connected to a 100 nF block capacitor connected between pin

VMID and ground

31

RSTPD

I

reset and power-down input:

HIGH: the internal current sinks are switched off, the oscillator is inhibited and

the input pads are disconnected

LOW (negative edge): start internal reset phase

32

OSCOUT

O

crystal oscillator output for the oscillator’s inverting amplifier

[1] Pin types: I = Input, O = Output, I/O = Input/Output, P = Power and G = Ground.

[2] The SLRC400 uses pin name SIGOUT for pin MFOUT. The CLRC632 functionality includes test functions for the SLRC400 using pin

MFOUT.

[3] These pins provide different functionality depending on the selected microprocessor interface type (see Section 9.1 on page 7 for

detailed information).

CLRC632

Product data sheet

COMPANY PUBLIC

All information provided in this document is subject to legal disclaimers.

Rev. 3.7 — 27 February 2014

073937

© NXP Semiconductors N.V. 2014. All rights reserved.

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