LC72700G View Datasheet(PDF) - SANYO -> Panasonic

Part Name

Description

Manufacturer

LC72700G

Mobile FM Multiplex Broadcast Receiver LSI

SANYO -> Panasonic 

LC72700E, LC72700G

Circuit Operation at Reset

1. Reset Signal

The reset operation is executed by holding the RST pin input level under VIL for 300 ns or longer when the power-

supply voltage (VDD) is over 3.4 volts. (See the figure.)

The reset operation is necessary to run this LSI.

VDD voltage

RST

2. Pin Outputs during a Reset

Low-level outputs: ...FILCK (1), CLK (5), DAT0 (13) to DAT7 (20), BCLOCK (21), FCLOCK (22), BL-CK (23),

FC-CK (24), D0 (32)

High-level outputs: ...RDY (26), RDYO (27), INT-R (35), XOUT (47)

Note: In serial mode, the DAT0 to DAT7 pins are held at the low level at all times. In parallel mode, these pins

output low levels during a reset.

3. Reset Operating Ranges

The output pins are stipulated to operate as described in item 2 above according to a reset signal. All the LSI internal

registers go the reset state. While the shift registers for 1T and 2T delay also go to the reset state, memory cells are

not affected. However, since the memory refresh operation is stopped, data cannot be maintained. The crystal

oscillator circuit is not stopped.

4. Data Input Following a Reset

The serial or the parallel input control circuit becomes capable of operating (accepting data) one clock cycle (about

278 ns at 3.6 MHz: i.e., the LSI's main clock) after the reset completes.

Output Data (basic operation concerning error correction)

Error correction using (272, 190) codes is performed for every block (272 bits) of received data. Data is output

immediately after error correction. This is referred to as horizontal correction. If the data could not be corrected by

horizontal correction, correction is performed in field units using product codes. This is referred to as vertical correction.

Since the horizontal correction output is output for each received block, it is an effective scheme for applications in

which the received data is desired quickly, such as in synchronous broadcasting. Vertical correction is only performed

when frame synchronization is achieved. Also, vertical correction is not performed when all the packet (block) data has

been completely corrected by horizontal correction. Since vertical correction is performed after one frame (272 blocks)

of data has been accumulated, normally about 5 seconds is required from data reception to the output of corrected data.

When post-horizontal correction data is output, all data blocks, including the parity block, are output. Post-vertical

correction output data does not include parity block data, but rather only the data in the data blocks (190 blocks of data)

is output. Note that when either frame synchronization is not achieved or horizontal correction completes and vertical

correction is not performed, the data that is output could be called post-vertical correction data. However, the content of

that data will be identical to post-horizontal correction data.

No. 4870-10/14

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