LC72700G View Datasheet(PDF) - SANYO -> Panasonic

Part Name

Description

Manufacturer

LC72700G

Mobile FM Multiplex Broadcast Receiver LSI

SANYO -> Panasonic 

LC72700E, LC72700G

Parallel Mode Data I/O Methods

Data is input and output using the parallel data interface I/O pins, INT-R (pin 35), RE (pin 25), RDY (pin 26), RDY0

(pin 27) and DATn (pins 13 to 20).

1. Basic Data Output Procedure

(1) Interrupt handling starts on the falling edge of INT-R.

(2) Set RE low.

(3) RDY goes low temporarily and then goes high on output ready.

(4) After RDY goes high, read in the data from DATn.

(5) Return RE to high.

Repeat steps (2) to (5) until 36 bytes of data have been read in.

Note: The period that RDY is low is 2.2 µs (typical). The CPU does not need to monitor RDY if it can adjust its

timing. Also, RDY0 is a signal that goes low when output is ready and goes high when RE returns to high.

The software logic for data acquisition can be simplified if the RDY (or RDY0) signal is input to the CPU

WAIT pin.

2. Parallel Data Output Timing

INT-R

3. Parallel Data Output Timing Stipulations

4. Data Input in Parallel Mode

To store data in parallel mode, set the internal register address of the data to be stored in PORT0 to PORT2 (pins 38 to

40) and set the PST pin (pin 37) low. Then input the data to DATn (pins 13 to 20). The PORT0 to PORT2 inputs and the

data to be stored are acquired by the LSI on the rising edge of the PST signal. When the PST pin is low, the DAT0 to

DAT7 pins function as input pins. Note that the PST pin data store cycle must be 1 µs or longer.

See the section on page 6 serial data I/O for notes and terminology descriptions concerning the data stored.

No. 4870-8/14

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