PEB20321 View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

PEB20321

MUNICH32X Multichannel Network Interface Controller for HDLC

Infineon Technologies 

PEB 20321

PEF 20321

Figure 83

Figure 84

Figure 85

Figure 86

Figure 87

Figure 88

Figure 89

Figure 90

Figure 91

Figure 92

Figure 93

Figure 94

Figure 95

Figure 96

Figure 97

Figure 98

Figure 99

Figure 100

Figure 101

Figure 102

Figure 103

Figure 104

Figure 105

Figure 106

Figure 107

Figure 108

Figure 109

Figure 110

Figure 111

Figure 112

Figure 113

Channel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Decoding of Peripheral Queue Interrupt Vectors . . . . . . . . . . . . . . . . 320

Block Diagram of Test Access Port and Boundary Scan . . . . . . . . . . 322

Power-up and Power-down Scenarios. . . . . . . . . . . . . . . . . . . . . . . . 329

Power-Failure Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 335

PCI Output Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . 335

PCI Input Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . . 336

PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

PCI Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

Master Single READ Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Master Burst WRITE/READ Access . . . . . . . . . . . . . . . . . . . . . . . . . .342

LBI Slave: Address Timing in Multiplexed Mode . . . . . . . . . . . . . . . . 344

LBI Slave: Address Timing in Non-Multiplexed Mode . . . . . . . . . . . . 344

LBI Slave: Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

LBI Slave: Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

LBI Master: Read Cycle Timing in Demultiplexed Mode . . . . . . . . . . 348

LBI Master: Write Cycle Timing in Demultiplexed Mode . . . . . . . . . . 348

LBI Master: Read Cycle Timing in Multiplexed Mode . . . . . . . . . . . . 349

LBI Master: Write Cycle Timing in Multiplexed Mode. . . . . . . . . . . . . 349

LBI Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

PCM Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

SSC Serial Interface Timing (Master) . . . . . . . . . . . . . . . . . . . . . . . . 356

Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

Ideal System, E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

Typical System, E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Ideal System, T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Typical System, T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Data Sheet

14

2001-02-14

Share Link: