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T8532-JL-TR View Datasheet(PDF) - Agere -> LSI Corporation

Part Name
Description
Manufacturer
T8532-JL-TR
Agere
Agere -> LSI Corporation Agere
T8532-JL-TR Datasheet PDF : 48 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Preliminary Data Sheet
November 2000
T8531/T8532 Multichannel Programmable
Codec Chip Set
General Description (continued)
T8531 Description
As shown in Figure 4, the T8531 contains a digital signal processor (DSP) engine surrounded by a customized
input/output frame. The I/O frame performs the µ-law or A-law conversion as well as the decimation and interpola-
tion functions needed to interface the sigma-delta bit streams to the digital signal processor engine. The sigma-
delta converters operate at a 1.024 MHz sample rate, while the signal processor operates at 16 ksamples/s. A key
function of the I/O frame is to control the timing of the digital data going to the signal processor so that group delay
is minimized.
The I/O frame also contains an integrated phase-locked loop which synthesizes all the required internal clocks for
the chip set.
The microcontroller interface is used to run the ROM routines and to download the gain, filter, and balance network
settings, powerup/powerdown commands, time-slot assignments, digital loopback settings, and commands for the
T8532 octal chips.
JTAG
HDS
PLL
CLOCK
SYNTHESIZER
SYSTEM PCM INTERFACE
DATA TRANSFER
µ/A-LAW CONVERTER
DIGITAL
SIGNAL
PROCESSING
ENGINE
DSP
ROM
DSP
RAM
MICRO-
PROCESSOR
CONTROL
INTERFACE
TSA
DECIMATOR
INTERPOLATOR
T8532 OVERSAMPLED INTERFACE
T8532 CONTROL INTERFACE
OSDX/R[3:0]
Figure 4. T8531 Block Diagram
UPCS
UPCK
UPDI
UPDO
HIGHZB
RSTB
T_SYNC
TSTCLK
TEST
VDD
VSS
0505(F)
Lucent Technologies Inc.
5

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