MC14560BD View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MC14560BD

NBCD Adder

Motorola => Freescale 

Table 1. Sum = A + B + C

Binary Sums

Decimal Corrected

Numbers Binary Sums

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

Non valid

1101

BCD

1110

representation

1111

0000 + Carry

0001 + Carry

0010 + Carry

0011 + Carry

0

0000

1

0001

2

0010

3

0011

4

0100

5

0101

6

0110

7

0111

8

1000

9

1001

10

0000 + Carry

11

0001 + Carry

12

0010 + Carry

13

0011 + Carry

14

0100 + Carry

15

0101 + Carry

16

0110 + Carry

17

0111 + Carry

18

1000 + Carry

19

1001 + Carry

6,941

+

5,870

THOUSANDS

0110

0101

ADDITION AND SUBTRACTION OF SIGNED NBCD

NUMBERS

Using MC14560 NBCD Adders and MC14561 9’s Comple-

menters, a sign and magnitude adder/subtracter can be con-

figured (Figure 5). Inputs A and B are signed positive (AS, BS

= “0”) or negative (AS, BS = “1”). B is added to or subtracted

from A under control of an Add/Sub line (subtraction = “1”).

The result, R, of the operation is positive signed, positive

signed with overflow, negative signed, or negative signed

with overflow. Add/subtract time is typically 0.6 + 0.4n µs for

n decades.

An exclusive–OR of Add/Sub line and BS produces B′,

which controls the B complementers. If BS, the sign of B, is a

logical “1” (B is negative) and the Add/Sub line is a “0” (add

B to A), then the output of the exclusive–OR (BS′) is a logical

“1” and B is complemented. If BS = “1” and Add/Sub = “1”, B

is not complemented since subtracting a negative number is

the same as adding a positive number. When Add/Sub is a

“1” and BS = “0”, BS′ is a “1” and B is complemented. The A

complementer is controlled by the A sign bit, AS. When AS =

“1”, A is complemented.

HUNDREDS

1001

1000

TENS

0100

0111

UNITS

0001

0000

4 BIT BINARY ADDERS

ADDER

Cin 1

ADDER

Cin 1

ADDER

Cin 0

ADDER

DIGIT BINARY SUMS

1011

1 0001

1011

0001

BINARY SUMS WITH

1100

1 0010

1011

0001

CARRY FROM CONVERTERS

CODE CONVERTERS

CORRECTED SUM

12,811

A

B

Cout

Cout

Cout

1 0010

1000

0001

Figure 4. Unsigned NBCD Addition Algorithm

Cout

0001

A1

B1

A2

B2

An

Bn

Cin

4 BIT BINARY FULL ADDER

BINARY TO NBCD

CODE CONVERTER

Cout

RESULT, R

(a) MC14560 Block Diagram

Cin

Cout

MC14560

R1

Cin

Cout

MC14560

Cin

Cout

MC14560

R2

Rn

Typical Add Time = 0.1 + 0.2n µs

where n = Number of Decades

(b) n–Decade Adder

OVERFLOW

Figure 5. Addition of Unsigned NBCD Numbers

MC14560B

6

MOTOROLA CMOS LOGIC DATA

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