DA1845JST Просмотр технического описания (PDF) - Analog Devices
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DA1845JST Datasheet PDF : 40 Pages
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AD1845
XCTL1:0
External Control. The state of these bits is reflected on the XCTL1:0 pins of the AD1845.
0
Logic LO on XCTL1:0 pins
1
Logic HI on XCTL1:0 pins
This register’s initial state after reset is “00xx xx00.”
Test and Initialization Register (IXA3:0 = 11)
IXA3:0
11
Data 7
COR
Data 6
PUR
Data 5
ACI
Data 4
DRS
Data 3
ORR1
Data 2
ORR0
Data 1
ORL1
Data 0
ORL0
ORL1:0
ORR1:0
DRS
ACI
PUR
COR
Overrange Left Detect. These bits indicate the overrange on the left capture channel. These bits change on
a sample-by-sample basis, and are read-only.
ORL1
0
0
1
1
ORL0
0
1
0
1
Less than –1 dB underrange
Between –1 dB and 0 dB underrange
Between 0 dB and +1 dB overrange
Greater than +1 dB overrange
Overrange Right Detect. These bits indicate the overrange on the right capture channel. These bits change
on a sample-by-sample basis, and are read-only.
ORR1
0
0
1
1
ORR0
0
1
0
1
Less than –1 dB underrange
Between –1 dB and 0 dB underrange
Between 0 dB and +1 dB overrange
Greater than +1 dB overrange
Data Request Status. This bit indicates the current status of the PDRQ and CDRQ pins of the AD1845.
0
CDRQ and PDRQ are presently inactive (LO)
1
CDRQ or PDRQ are presently active (HI)
Autocalibrate-In-Progress. This bit indicates the state of autocalibration or a recent exit from Mode Change
Enable (MCE). This bit is read-only.
0
Autocalibration is not in progress
1
Autocalibration is in progress or MCE was exited within the last 128 sample periods
Playback Underrun. This bit is set when the playback FIFO is empty and after the next valid sample has been
played back. If this condition exists, DACZ determines the DAC playback value. In MODE1, DACZ is always set
and returns a midscale value.
Capture Overrun. This bit is set when the capture FIFO is full and an additional sample has been captured. The
sample being read will not be overwritten by the new sample. The new sample will be ignored. This bit changes on
a sample by sample basis.
The occurrence of a PUR and/or COR is designated in the Status Register’s Sample Overrun/Underrun (SOUR) bit. The SOUR bit
is the logical OR of the COR and PUR bits. This enables a polling host CPU to detect an overrun/underrun condition while check-
ing other status bits.
This register’s initial state after reset is “0000 0000.”
Miscellaneous Control Register (IXA3:0 = 12)
IXA3:0
12
Data 7
MID
Data 6
MODE2
Data 5
res
Data 4
BUF8
Data 3
ID3
Data 2
ID2
Data 1
ID1
Data 0
ID0
ID3:0
BUF8
res
AD1845 Revision ID. These four bits define the revision level of the AD1845. The AD1845 will have ID =
“1010.” These bits are read-only.
Parallel Interface Bus Transceiver Current Buffer Drive. The AD1845 can be programmed to provide a current
drive of 16 mA or 8 mA.
0
16 mA current drive.
1
8 mA current drive.
Reserved for future expansion. Always write 0s to these bits.
REV. C
–21–
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