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DA1845JST

Parallel-Port 16-Bit SoundPort® Stereo Codec

Analog Devices 

AD1845

Figure 30 shows ac-coupled line outputs. The resistors are used

to center the output signals around analog ground. If dc-cou-

pling is desired, VREF could be used with op amps as mentioned

above, if desired.

L_OUT

1␮F

47k⍀

R_OUT

1␮F

47k⍀

Figure 30. Line Output Connections

A circuit for headphone drive is illustrated in Figure 31. Drive is

supplied by +5 V operational amps. The circuit shown ac

couples the headphones to the line output.

L_OUT

V_REF

10k⍀

8.66k⍀

HEADPHONE

LEFT

470␮F

SSM-2135

XTAL1I

XTAL1O

20–64pF

24.576 MHz

20–64pF

Figure 34. Crystal Connections

Note: XTAL2I and XTAL2O, are not used in the AD1845.

Analog Devices also recommends a pull-down resistor for

PWRDWN.

Good, standard engineering practices should be applied for

power-supply decoupling. Decoupling capacitors should be

placed as close as possible to package pins. If a separate analog

power supply is not available, we recommend the circuit shown

in Figure 35 for using a single +5 V supply. Ferrite beads suffice

for the inductors shown (typically 600 Ω at 100 MHz). This

circuitry should be as close to the supply pins as is practical.

+5V

SUPPLY

FB

0.1␮F

+

–10␮F

0.1␮F

0.1␮F

+

10␮F–

VDD

VDD

0.1␮F

R_OUT

10k⍀

HEADPHONE

RIGHT

470␮F

8.66k⍀

Figure 31. Headphone Drive Connections

Figure 32 illustrates reference bypassing. VREF_F should only be

connected to its bypass capacitors.

VREF_F

1.0µF

10µF

VREF

10µF

Figure 32. Voltage Reference Bypassing

Figure 33 illustrates signal-path filtering capacitors, L_FILT

and R_FILT. The AD1845 must use 1.0 µF capacitors; the

AD1845 will not perform properly with 1000 pF capacitors.

The 1.0 µF capacitors required by the AD1845 can be of any

type.

L_FILT R_FILT

1.0µF

1.0µF

Figure 33. External Filter Capacitor Connections

The crystal shown in the crystal connection circuitry of Fig-

ure 34 should be 24.576 MHz, fundamental-mode and parallel-

tuned. Note that using the exact data sheet frequencies is not

required and that external clock sources can be used to over-

drive the AD1845’s internal oscillators. (See the description of

the CFS2:0 control bits above.) If using an external clock source,

apply it to the crystal input pins while leaving the crystal output

pins unconnected. Attention should be paid to providing low

jitter external input clocks.

FB

0.1␮F

+

–10␮F

VDD

0.1␮F 0.1␮F

VCC

VCC

Figure 35. Recommended Power Supply Bypassing

GROUNDING AND LAYOUT

Analog Devices recommends a split ground plane as shown in

Figure 36. The analog plane and the digital plane are connected

directly under the AD1845. Splitting the ground plane directly

under the SoundPort Codec is optimal because analog pins will

be located above the analog ground plane and digital pins will

be located directly above the digital ground plane for the best

isolation.

Other schemes may also yield satisfactory results. If the split

ground plane recommended here is not possible, the AD1845

should be entirely over the analog ground plane with the op-

tional 74_245 transceiver over the digital plane.

Some manufacturers of compatible devices differentiate between

digital supply pins used to power internal logic and digital sup-

ply pins used to power the ISA bus driver. Their recommended

layout suggests connecting the internal logic supply pins to the

analog supply. A potential problem can occur if the layout con-

nects digital supply pins to the analog supply. Connecting some

of the digital supply pins to one supply and some of the digital

supply pins to a different supply can create an internal short

between the two different +5 V supplies.

REV. C

–35–

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