AD9853AS Просмотр технического описания (PDF) - Analog Devices

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AD9853AS

Programmable Digital QPSK/16-QAM Modulator

Analog Devices 

AD9853

Table II. Control Register Functional Assignment

Register

Address

(Note 1) D7

DATA

D6

D5

D4

D3

D2

D1

D0

00h

MSB

Value of K (Message Length in Bytes) for Reed-Solomon Encoder, where 1610 ≤ K ≤ 25510 (Note 2)

LSB

01h

MSB

The Number of Correctable Byte

LSB

Errors (t) for the Reed-Solomon

Encoder, where 0 ≤ t ≤ 1010.

For t = 0, the RS encoder is

effectively disabled.

Randomizer

Insertion

0 = After RS

1 = Before RS

Randomizer Length

002 = 6 Bit

012 = 15 Bit

102 = Randomizer OFF

112 = Randomizer OFF

(Note 3)

02h

MSB

Lower Eight Bits of Seed Value for 15-Bit Randomizer (Not Used for 6-Bit Randomizer)

LSB

03h

MSB

Upper Seven Bits of Seed Value for 15-Bit Randomizer

LSB

– OR –

Seed Value for 6-Bit Randomizer (D1 not used in this case).

04h

MSB

Preamble Length (L) where 0 ≤ L ≤ 96 Bits (Note 4)

LSB

05h

Modulation Mode

0002 = QPSK , 0012 = DQPSK, 0102 = 16-QAM

0112 = D16-QAM , 1002 = FSK

OBSOLETE 06h

The MSB of the preamble always resides in D7 of Address 11h and is the first preamble bit to be clocked out of the device during transmission of

:

a packet. Up to 96 bits of preamble are available as specified in Register 04h. Unused bits are don’t care for L < 96.

11h

MSB

Preamble Data. (Note 5)

12h

13h

14h

MSB

MSB

Interpolator #1: RATE

Rate Change Factor (R) where 310 ≤ R ≤ 3110

MSB

Interpolator #2: RATE

Rate Change Factor (R) where 210 ≤ R ≤ 6310

Interpolator #1: SCALE

LSB

LSB

LSB

2× Multiplier

0 = OFF

1 = ON

15h6

MSB

Interpolator #2: SCALE

LSB

16h

:

19h

MSB

Frequency Tuning Word #1

LSB

FSK Mode: Specifies the “space” frequency (F0).

All Other Modes: Specifies the carrier frequency.

1Ah

:

1Dh

MSB

Frequency Tuning Word #2

LSB

FSK Mode: Specifies the “mark” frequency (F1).

(Addresses 1Ah–1Dh are only valid for FSK mode.)

1Eh5

1Fh

MSB-2

MSB0

MSB-3

MSB-1

10-Bit FIR End Tap Coefficient, a0

LSB0

<— —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ Unused Bits —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —>

:

:

FIR Intermediate Tap Coefficients, a1 – a19

:

46h

47h

48h

(Note 7)

MSB-2

MSB20

Spectrum

0 = I × Cos + Q × Sin

1 = I × Cos – Q × Sin

MSB-3

MSB-1

Digital Power

0 = Normal

1 = Shutdown

10-Bit FIR Center Tap Coefficient, a20

LSB20

<— —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ Unused Bits —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —>

6× RefClk

0 = Off

1 = On

PLL Mode

0 = Awake

1 = Sleep

DAC Mode

0 = Awake

1 = Sleep

49h

(Note 8)

MSB

AD8320 Cable Driver Gain Control Byte (GCB)

The absolute gain, AV, of the AD8320 is given by: AV = 0.316 + 0.077 × GCB (where 0 ≤ GCB ≤ 25510)

LSB

NOTES

1The 8-bit Register Address is preceded by an 8-bit Device Address, which is given by

000001XY, where the value of Bits X and Y are determined as follows:

X

Voltage Applied to Pin 6

Y

Desired Register Function

0

GND

0

WRITE

1

+VS

1

READ

2This register must be loaded with a nonzero value even if the RS encoder has been

disabled by setting T = 0 in register 01h.

3Unused regions are don’t care bit locations.

4If a preamble is not used this register must be initialized to a value of 0 by the user.

5Addresses 06h–011h and 1Eh–47h are write only.

6Readback of register 15h results in a value that is 2× the actual programmed value.

This is a design error in the readback function.

7Assertion of RESET (Pin 32) sets the contents of this register to 0.

8Registers 0h–48h may be written to using a single register address followed by a

contiguous data sequence (see Figure 27). Register 49h, however, must be written to

individually; i.e., a separately addressed 8-bit data sequence.

–6–

REV. C

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