M66850FP Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC

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производитель

M66850FP

SRAM TYPE FIFO MEMORY

MITSUBISHI ELECTRIC  

• Write Cycle Timing

MITSUBISHI <DIGITAL ASSP>

M66850J/FP, M66851J/FP

M66852J/FP, M66853J/FP

SRAM TYPE FIFO MEMORY

WCLK

D0-D8

WEN1

tCLKH

tCLK

tCLKL

tDS tDH

DATA IN VALID

tENS

tENH

NO OPERATION

WEN2/(if Applicable)

FF

tSKEW1 (1)

RCLK

tWFF

NO OPERATION

tWFF

REN1

REN2

NOTE :

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle.

If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state untill

the next WCLK edge.

7

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