STPCI2GDYI Просмотр технического описания (PDF) - STMicroelectronics

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STPCI2GDYI

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

■ TFT Interface

■ Supports ISA hidden refresh.

■ Programmable panel size up to 1024 by 1024 ■ Buffered DMA & ISA master cycles to reduce

pixels.

bandwidth utilization of the PCI and Host

■ Support for VGA and SVGA active matrix TFT

bus.

flat panels with 9, 12, 18-bit interface (1 pixel

per clock).

■ Local Bus interface

■ Support for XGA and SXGA active matrix ■ Multiplexed with ISA/DMA interface.

TFT flat panels with 2 x 9-bit interface (2 ■ Low latency asynchronous bus

pixels per clock).

■ 16-bit data bus with word steering capability.

■ Programmable image positionning.

■ Programmable timing (Host clock granularity)

■ Programmable blank space insertion in text ■ 4 Programmable Flash Chip Select.

mode.

■ 8 Programmable I/O Chip Select.

■ Programmable horizontal and vertical image ■ I/O device timing (setup & recovery time)

expansion in graphic mode.

programmable

■ One fully programmable PWM (Pulse Width ■ Supports 32-bit Flash burst.

Modulator) signals to adjust the flat panel

) brightness and contrast.

t(s ■ Supports PanelLinkTM high speed serial

transmitter externally for high resolution

uc panel interface.

rod ■ PCI Controller

P ■ Compatible with PCI 2.1 specification.

te ■ Integrated PCI arbitration interface. Up to 3

masters can connect directly. External logic

le allows for greater than 3 masters.

so ■ Translation of PCI cycles to ISA bus.

b ■ Translation of ISA master initiated cycle to

O PCI.

- ■ Support for burst read/write from PCI master.

) ■ PCI clock is 1/2, 1/3 or 1/4 Host bus clock.

ct(s ■ ISA master/slave

u ■ Generates the ISA clock from either

rod 14.318MHz oscillator clock or PCI clock

■ Supports programmable extra wait state for

P ISA cycles

te ■ Supports I/O recovery time for back to back

le I/O cycles.

o ■ Fast Gate A20 and Fast reset.

s ■ Supports the single ROM that C, D, or E.

Obblocks shares with F block BIOS ROM.

■ 2-level hardware key protection for Flash boot

block protection.

■ Supports 2 banks of 32MB flash devices with

boot block shadowed to 0x000F0000.

■ Reallocatable Memory space Windows

■ EIDE Interface

■ Supports PIO

■ Transfer Rates to 22 MBytes/sec

■ Supports up to 4 IDE devices

■ Concurrent channel operation (PIO modes) -

4 x 32-Bit Buffer FIFOs per channel

■ Support for PIO mode 3 & 4.

■ Individual drive timing for all four IDE devices

■ Supports both legacy & native IDE modes

■ Supports hard drives larger than 528MB

■ Support for CD-ROM and tape peripherals

■ Backward compatibility with IDE (ATA-1).

■ Integrated Peripheral Controller

■ 2X8237/AT compatible 7-channel DMA

controller.

■ 2X8259/AT compatible interrupt Controller. 16

interrupt inputs - ISA and PCI.

■ Three 8254 compatible Timer/Counters.

■ Co-processor error support logic.

■ Supports external RTC (Not in Local Bus

■ Supports flash ROM.

Mode).

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