AD9772EB Просмотр технического описания (PDF) - Analog Devices
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AD9772EB Datasheet PDF : 30 Pages
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AD9772–SPECIFICATIONS
DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = +0 V, DVDD = +3 V, IOUTFS = 20 mA, unless
otherwise noted)
Parameter
Min
Typ
Max
Units
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current1
Logic “0” Current
Input Capacitance
2.1
3
V
0
0.9
V
–10
+10
µA
–10
+10
µA
5
pF
CLOCK INPUTS
Input Voltage Range
Common-Mode Voltage
Differential Voltage
0
3
V
0.75
1.5
2.25
V
0.5
1.5
V
PLL CLOCK ENABLED—FIGURE 1a
Input Setup Time (tS)
1.0
ns
Input Hold Time (tH)
2.5
ns
Latch Pulsewidth (tLPW)
1.5
ns
PLL CLOCK DISABLED—FIGURE 1b
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW)
CLK/PLLLOCK Delay (tOD)
1.0
ns
2.5
ns
1.5
ns
5
ns
NOTES
1MOD1 and MOD0 have typical input currents of 120 µA while SLEEP has a typical input current of 15 µA.
Specifications subject to change without notice.
DB0–DB13
CLK+ – CLK–
tH
tS
tLPW
DB0–DB13
PLLLOCK
CLK+ – CLK–
tH
tS
tOD
tLPW
IOUTA
OR
IOUTB
tPD
tST
0.025%
0.025%
IOUTA
OR
IOUTB
tPD
tST
0.025%
0.025%
Figure 1a. Timing Diagram—PLL Clock Multiplier Enabled Figure 1b. Timing Diagram—PLL Clock Multiplier Disabled
–4–
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