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3110KRC

Triple Video D/A Converters 3 x 10 bit, 150 Ms/s

Fairchild Semiconductor

3110KRC Datasheet PDF : 11 Pages

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DATA SHEET

FMS3110/3115

Applications Discussion

Figure 5 illustrates a typical FMS3110/3115 interface cir-

cuit. In this example, an optional 1.2 Volt bandgap reference

connected to the VREF output, overriding the internal volt-

age reference source.

Grounding

It is important that the FMS3110/3115 power supply is well-

regulated and free of high-frequency noise. Careful power

supply decoupling will ensure the highest quality video sig-

nals at the output of the circuit. The FMS3110/3115 has sep-

arate analog and digital circuits. To keep digital system noise

from the D/A converter, it is recommended that power supply

voltages (VDD) come from the system analog power source

and all ground connections (GND) be made to the analog

ground plane. Power supply pins should be individually

decoupled at the pin.

Printed Circuit Board Layout

Designing with high-performance mixed-signal circuits

demands printed circuits with ground planes. Overall system

performance is strongly inﬂuenced by the board layout.

Capacitive coupling from digital to analog circuits may

result in poor D/A conversion. Consider the following sug-

gestions when doing the layout:

1. Keep the critical analog traces (VREF, IREF, COMP,

IOS, IOR, IOG) as short as possible and as far as possi-

ble from all digital signals. The FMS3110/3115 should

be located near the board edge, close to the analog out-

put connectors.

2. Power plane for the FMS3110/3115 should be separate

from that which supplies the digital circuitry. A single

power plane should be used for all of the VDD pins. If

the power supply for the FMS3110/3115 is the same as

that of the system's

digital circuitry, power to the FMS3110/3115 should be

decoupled with 0.1µF and 0.01µF capacitors and iso-

lated with a ferrite bead.

3. The ground plane should be solid, not cross-hatched.

Connections to the ground plane should have very short

leads.

4. If the digital power supply has a dedicated power plane

layer, it should not be placed under the FMS3110/3115,

the voltage reference, or the analog outputs. Capacitive

coupling of digital power supply noise from this layer to

the FMS3110/3115 and its related analog circuitry can

have an adverse effect on performance.

5. CLK should be handled carefully. Jitter and noise on

this clock will degrade performance. Terminate the

clock line carefully to eliminate overshoot and ringing.