AN5891K Просмотр технического описания (PDF) - Panasonic Corporation
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AN5891K Datasheet PDF : 27 Pages
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AN5891K
Technical Data (continued)
y I2C-bus
2. Transmission Message
SDA
SCL
START condition
Slave address
ACK
Sub address
ACK
Data
ACK STOP
/ condition
10000010
00000010
00010010
e ) 8
2
0
2
c type Fig.1 Example of transmission message
1
2
n dle stageo.ntinued For transmission messages, both SCL and SDA are transferred in the form of synchronized serial transmission.
a e cyc isc SCL is a clock of a specific frequency, and SDA indicates address data for controlling the receiving side and is transferred in
life d, d parallel, being synchronized with SCL.
n u ct pe Data is transferred in principle in 3 octets (bytes), and each one octet (one octet = 8 bits) includes one acknowledge bit.
te tin Produ ued ty Frame structure is described below.
four ontin (a) START condition
ing isc The receiver becomes possible to receive data when SDA changes from High to Low while SCL is High.
in n follow ned d (b) STOP condition
es pla The receiver halts receiving when SDA changes from Low to High while SCL is High.
a o includ type, (c) Slave address
c ed ce This is an address which is determined for each device. If other device address is sent, receiving will be halted.
M is ntinu tenan (d) Sub address
isco ain This is an address which is determined for each function.
ce/D pe, m (e) Data
D an ty This is control data.
ainten nance (f) Acknowledge bit
M te This is a bit by which the master acknowledges that data was successfully received in each octet. Master sends the High
ain signal and the receiver sends back the Low signal as shown in Figure 1 with dotted line, causing the master to
m acknowledge the reception by the receiver. If the Low signal is not returned, communication will be halted.
(planed Except START and STOP conditions, SDA does not change while SCL is High.
SDB00169AEB
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