INIC-1511 Просмотр технического описания (PDF) - Unspecified

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INIC-1511

USB to PATA Bridge

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INIC-1511 (Preliminary)

out for outgoing data or abort the DMA operation for incoming data.

This bit is self-cleared by hardware.

6.2.13 Channel Clear Register (cmdCtl_Clr, 0x0B3)

Field name

Reserved

CmdTx4Run

(for HID_out)

CmdTx3Run

(for CSW_out)

Reserved

CmdTx1Run

(for Control_out)

Reserved

CmdTx1Run

(for CBW)

CmdTx1Run

(for Setup-Packet)

rscu bit # reset Description

r

7

7’b0 Reserved

rwu 6

1’b0 When the Clear register is set by software, the corresponding channel is

cleared.

rwu 5

1’b0 When the Clear register is set by software, the corresponding channel is

cleared.

r

4

1’b0 Reserved

rwu 3

1’b0 When the Clear register is set by software, the corresponding channel is

cleared.

r

2

1’b0 Reserved

rwu 1

1’b0 When the Clear register is set by software, the corresponding channel is

cleared.

rwu 0

1’b0 When the Clear register is set by software, the corresponding channel is

cleared.

6.2.14 sgDma Control Register (sgCtl_Set, 0x0B4) (sgCtl_Clr, 0x0B5)

Field name

Reserved

Sg0Run

rscu

r

rwu

bit #

7:1

0

reset

7’b0

1’b0

Description

Reserved.

When Set register is set by software, the corresponding channel is ready to

be transmitted. The hardware clears these bits when the transfer is completed.

Software can set bit[3:0] on Clear register to clear the corresponding bit.

When Clear register is written by software, the DMA channels will be reset to

idle. (USB bulk transfer will only use sg0Run)

6.2.15 ATA Control register (AtaCtl, 0x0B6)

Field name

rscu bit # reset Description

AtaDMAEn

rw 7

1’b1 When 1, ataDMA is enabled.

pioReq/pioGnt

rw 6

1’b0 Write 1 for PIO request. PIO grant status when read.

dmaMode

rw 5

1’b0 0-2: DMA mode 0 - 2

rw 4

1’b0 4-7: UDMA mode 2, 3, 4 and 5 (up to uDMA100)

rw 3

1’b0

pioMode

rw 2

1’b0 0-4: PIO mode 0-4

rw 1

1’b0

rwu 0

1’b0

6.2.16 ATA Control/Status register (ataStatus, 0x0B7)

Field name

Reserved

AtaCh0En

PioXEn

rscu bit # reset Description

r

7

1’b0 Reserved

rw 6 1’b0 Ata Channel Enable.

rw 5

1’b0 PIO transfer engine enable. When set, the PIO engine will transfer data

to/from the ATA bus using PIO transfer mechanism.

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