IT8502 Просмотр технического описания (PDF) - ITE Tech. INC.
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Компоненты Описание
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IT8502 Datasheet PDF : 398 Pages
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Contents
6.4.1 Overview ......................................................................................................................... 95
6.4.2 Features .......................................................................................................................... 95
6.4.3 Functional Description ..................................................................................................... 95
6.4.3.1 Wake-Up Status .................................................................................................. 95
6.4.3.2 Wake-Up Events.................................................................................................. 96
6.4.3.3 Wake-Up Output Events ...................................................................................... 96
6.4.3.4 Other SWUC Controlled Options.......................................................................... 97
6.4.4 Host Interface Registers................................................................................................... 98
6.4.4.1 Wake-Up Event Status Register (WKSTR)........................................................... 98
6.4.4.2 Wake-Up Event Enable Register (WKER) ............................................................ 99
6.4.4.3 Wake-Up Signals Monitor Register (WKSMR)...................................................... 99
6.4.4.4 Wake-Up ACPI Status Register (WKACPIR) ...................................................... 100
6.4.4.5 Wake-Up SMI Enable Register (WKSMIER) ...................................................... 100
6.4.4.6 Wake-Up IRQ Enable Register (WKIRQER) ...................................................... 101
6.4.5 EC Interface Registers ................................................................................................... 101
6.4.5.1 SWUC Control Status 1 Register (SWCTL1) ...................................................... 102
6.4.5.2 SWUC Control Status 2 Register (SWCTL2) ...................................................... 103
6.4.5.3 SWUC Control Status 3 Register (SWCTL3) ...................................................... 103
6.4.5.4 SWUC Host Configuration Base Address Low Byte Register (SWCBALR) ......... 103
6.4.5.5 SWUC Host Configuration Base Address High Byte Register (SWCBAHR)........ 103
6.4.5.6 SWUC Interrupt Enable Register (SWCIER) ...................................................... 104
6.4.5.7 SWUC Host Event Status Register (SWCHSTR)................................................ 105
6.4.5.8 SWUC Host Event Interrupt Enable Register (SWCHIER) .................................. 106
6.5 Keyboard Controller (KBC)......................................................................................................... 107
6.5.1 Overview ....................................................................................................................... 107
6.5.2 Features ........................................................................................................................ 107
6.5.3 Functional Description ................................................................................................... 107
6.5.4 Host Interface Registers................................................................................................. 108
6.5.4.1 KBC Data Input Register (KBDIR)...................................................................... 108
6.5.4.2 KBC Data Output Register (KBDOR) ................................................................. 108
6.5.4.3 KBC Command Register (KBCMDR) ................................................................. 109
6.5.4.4 KBC Status Register (KBSTR) ........................................................................... 109
6.5.5 EC Interface Registers ................................................................................................... 109
6.5.5.1 KBC Host Interface Control Register (KBHICR) ................................................. 110
6.5.5.2 KBC Interrupt Control Register (KBIRQR) .......................................................... 111
6.5.5.3 KBC Host Interface Keyboard/Mouse Status Register (KBHISR) ........................ 112
6.5.5.4 KBC Host Interface Keyboard Data Output Register (KBHIKDOR) ..................... 112
6.5.5.5 KBC Host Interface Mouse Data Output Register (KBHIMDOR) ......................... 112
6.5.5.6 KBC Host Interface Keyboard/Mouse Data Input Register (KBHIDIR) ................ 112
6.6 Power Management Channel (PMC) .......................................................................................... 113
6.6.1 Overview ....................................................................................................................... 113
6.6.2 Features ........................................................................................................................ 113
6.6.3 Functional Description ................................................................................................... 113
6.6.3.1 General Description ........................................................................................... 113
6.6.3.2 Compatible Mode .............................................................................................. 114
6.6.3.3 Enhanced PM mode .......................................................................................... 115
6.6.3.4 PMC2EX ........................................................................................................... 116
6.6.3.5 PMC3 ................................................................................................................ 117
6.6.4 Host Interface Registers................................................................................................. 117
6.6.4.1 PMC Data Input Register (PMDIR)..................................................................... 118
6.6.4.2 PMC Data Output Register (PMDOR) ................................................................ 118
6.6.4.3 PMC Command Register (PMCMDR) ................................................................ 118
6.6.4.4 Status Register (PMSTR) .................................................................................. 118
6.6.5 EC Interface Registers ................................................................................................... 120
6.6.5.1 PM Status Register (PMSTS)............................................................................. 121
6.6.5.2 PM Data Out Port (PMDO)................................................................................. 121
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IT8502E/F/G V0.7.7
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