EP1C12Q173I8 Просмотр технического описания (PDF) - Altera Corporation

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производитель

EP1C12Q173I8

Cyclone FPGA Family

Altera Corporation 

Cyclone Device Handbook, Volume 1

Table 4–52. Cyclone PLL Specifications (Part 2 of 2)

Symbol

fOUT (to global clock)

tOUT DUTY

tJITTER (1)

tLOCK (3)

fVCO

-

N, G0, G1, E

Parameter

PLL output frequency

(-6 speed grade)

PLL output frequency

(-7 speed grade)

PLL output frequency

(-8 speed grade)

Duty cycle for external clock

output (when set to 50%)

Period jitter for external clock

output

Time required to lock from end

of device configuration

PLL internal VCO operating

range

Minimum areset time

Counter values

Min

15.625

15.625

15.625

45.00

10.00

500.00

10

1

Max

405

320

275

55

±300 (2)

100

1,000

32

Unit

MHz

MHz

MHz

%

ps

μs

MHz

ns

integer

Notes to Table 4–52:

(1) The tJITTER specification for the PLL[2..1]_OUT pins are dependent on the I/O pins in its VCCIO bank, how many

of them are switching outputs, how much they toggle, and whether or not they use programmable current strength

or slow slew rate.

(2) fOUT ≥ 100 MHz. When the PLL external clock output frequency (fOUT) is smaller than 100 MHz, the jitter

specification is 60 mUI.

(3) fIN/N must be greater than 200 MHz to ensure correct lock detect circuit operation below –20 C. Otherwise, the PLL

operates with the specified parameters under the specified conditions.

4–30

Preliminary

Altera Corporation

January 2007

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