EP1C12T173C6 Просмотр технического описания (PDF) - Altera Corporation

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Компоненты Описание

производитель

EP1C12T173C6

Cyclone FPGA Family

Altera Corporation 

Cyclone Device Handbook, Volume 1

Figure 2–15. M4K RAM Block Control Signals

Dedicated

6

LAB Row

Clocks

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

clocken_a

alcr_a

renwe_b

clock_b

clock_a

renwe_a

alcr_b

clocken_b

Figure 2–16. M4K RAM Block LAB Row Interface

C4 Interconnects

Direct link

10

interconnect

to adjacent LAB

dataout

Direct link

interconnect

from adjacent LAB

M4K RAM

Block

Byte enable

Clocks

Control

Signals

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

R4 Interconnects

Direct link

interconnect

to adjacent LAB

Direct link

interconnect

from adjacent LAB

address datain

6

M4K RAM Block Local

Interconnect Region

LAB Row Clocks

2–24

Preliminary

Altera Corporation

January 2007

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