AD7714YRUZ Просмотр технического описания (PDF) - Analog Devices

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производитель

AD7714YRUZ

3 V/5 V, CMOS, 500 μA Signal Conditioning ADC

Analog Devices 

AD7714Y

Parameter

Y Versions

Units Conditions/Comments

LOGIC OUTPUTS (Continued))

VOH, Output High Voltage

Floating State Leakage Current

Floating State Output Capacitance13

Data Output Coding

TRANSDUCER BURNOUT14

Current

Initial Tolerance

Drift

DVDD – 0.6

± 10

9

Binary

Offset Binary

1

± 10

0.1

V min

µA max

pF typ

ISOURCE = 100 µA with DVDD = 3 V. Except for MCLK OUT12

Unipolar Mode

Bipolar Mode

µA nom

% typ

%/°C typ

SYSTEM CALIBRATION

Positive Full-Scale Calibration Limit15

Negative Full-Scale Calibration Limit15

Offset Calibration Limit16

Input Span16

(1.05 × VREF)/GAIN V max

–(1.05 × VREF)/GAIN V max

–(1.05 × VREF)/GAIN V max

0.8 × VREF/GAIN V min

(2.1 × VREF)/GAIN V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

GAIN Is the Selected PGA Gain (Between 1 and 128)

GAIN Is the Selected PGA Gain (Between 1 and 128)

GAIN Is the Selected PGA Gain (Between 1 and 128)

GAIN Is the Selected PGA Gain (Between 1 and 128)

POWER REQUIREMENTS

Power Supply Voltages

AVDD Voltage

+2.7 to +3.3 or

V

+4.75 to +5.25

V

For Specified Performance

DVDD Voltage

Power Supply Currents

AVDD Current

DVDD Current18

Power Supply Rejection19

Normal-Mode Power Dissipation18

+2.7 to +5.25

0.28

0.6

0.5

1.1

0.080

0.16

0.18

0.35

See Note 20

V

For Specified Performance

mA max

mA max

mA max

mA max

mA max

mA max

mA max

mA max

dB typ

AVDD = 3 V or 5␣ V. BST Bit of Filter High Register = 017, CLKDIS = 1

Typically 0.22 mA. BUFFER = 0 V. fCLK IN = 1␣ MHz or 2.4576␣ MHz

Typically 0.45 mA. BUFFER = DVDD. fCLK IN = 1␣ MHz or 2.4576␣ MHz

AVDD = 3 V or 5␣ V. BST Bit of Filter High Register = 117

Typically 0.38␣ mA. BUFFER = 0␣ V. fCLK IN = 2.4576␣ MHz

Typically 0.8␣ mA. BUFFER = DVDD. fCLK IN = 2.4576␣ MHz

Digital I/Ps = 0␣ V or DVDD. External MCLK IN, CLKDIS = 1

Typically 0.06␣ mA. DVDD = 3 V. fCLK IN = 1␣ MHz

Typically 0.13␣ mA. DVDD = 5␣ V. fCLK IN = 1␣ MHz

Typically 0.15␣ mA. DVDD = 3 V. fCLK IN = 2.4576␣ MHz

Typically 0.3 mA. DVDD = 5␣ V. fCLK IN = 2.4576␣ MHz

AVDD = DVDD = +3 V. Digital I/Ps = 0␣ V or DVDD. External MCLK IN

BST Bit of Filter High Register = 017

1.05

2.04

1.35

2.34

Normal-Mode Power Dissipation

2.1

3.75

3.1

4.75

Standby (Power-Down) Current21

18

Standby (Power-Down) Current21

10

mW max

mW max

mW max

mW max

mW max

mW max

mW max

mW max

µA max

µA max

Typically 0.84␣ mW. BUFFER = 0␣ V. fCLK IN = 1␣ MHz. BST Bit = 0

Typically 1.53␣ mW. BUFFER = +3 V. fCLK IN = 1␣ MHz. BST Bit = 0

Typically 1.11␣ mW. BUFFER = 0␣ V. fCLK IN = 2.4576␣ MHz. BST Bit = 0

Typically 1.9␣ mW. BUFFER = +3 V. fCLK IN = 2.4576␣ MHz. BST Bit = 0

AVDD = DVDD = +5␣ V. Digital I/Ps = 0␣ V or DVDD. External MCLK IN

Typically 1.75 mW. BUFFER = 0␣ V. fCLK IN = 1␣ MHz. BST Bit = 0

Typically 2.9 mW. BUFFER = +5␣ V. fCLK IN = 1␣ MHz. BST Bit = 0

Typically 2.6␣ mW. BUFFER = 0␣ V. fCLK IN = 2.4576␣ MHz. BST Bit = 0

Typically 3.75␣ mW. BUFFER = +5␣ V. fCLK IN = 2.4576␣ MHz. BST Bit = 0

External MCLK IN = 0 V or DVDD. Typically 9␣ µA. VDD = +5 V

External MCLK IN = 0 V or DVDD. Typically 4␣ µA. VDD = +3 V

NOTES

1Temperature range is as follows: Y Version: –40°C to +105°C.

2A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I to IV. This applies after calibration at the temperature of interest.

3Recalibration at any temperature will remove these drift errors.

4Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.

5Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.

6Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error—Unipolar Offset Error for unipolar ranges and Full-Scale Error—Bipolar Zero Error for

bipolar ranges.

7Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with background calibration.

8These numbers are guaranteed by design and/or characterization.

9The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.

10The input voltage range on the analog inputs is given here with respect to the voltage on the respective negative input of its differential or pseudo-differential pair. See Table VII for which

inputs form differential pairs.

11VREF = REF IN(+) – REF IN(–).

12These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.

13Sample tested at +25°C to ensure compliance.

14See Burnout Current section.

15After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.

16These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30␣ mV or go more negative than AGND␣ –␣ 30␣ mV. The offset calibration

limit applies to both the unipolar zero point and the bipolar zero point.

17For higher gains (≥8) at fCLK␣ IN = 2.4576␣ MHz, the BST bit of the Filter High Register must be set to 1. For other conditions, it can be set to 0.

18When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation will vary depending on the crystal or resonator

type (see Clocking and Oscillator Circuit section).

19Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter

notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz.

20PSRR depends on gain.

Gain

1

2

4

8–128

AVDD = 3 V

AVDD = 5 V

86 dB

90 dB

78 dB

78 dB

85 dB

84 dB

93 dB

91 dB

21If the external master clock continues to run in standby mode, the standby current increases to 150 µA typical with 5 V supplies and 75 µA typical with 3.3 V supplies. When using a crystal

or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or

resonator type (see Standby Mode section).

Specifications subject to change without notice.

–6–

REV. C

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