AGL060V5-QNG144 Просмотр технического описания (PDF) - Microsemi Corporation
Номер в каталоге
Компоненты Описание
производитель
AGL060V5-QNG144 Datasheet PDF : 250 Pages
| |||
5 – Datasheet Information
List of Changes
The following tables list critical changes that were made in each revision of the IGLOO datasheet.
Revision
Changes
Page
Revision 23
The "IGLOO Ordering Information" section has been updated to mention "Y" as "Blank" III
(December 2012) mentioning "Device Does Not Include License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43173).
The note in Table 2-189 · IGLOO CCC/PLL Specification and Table 2-190 · IGLOO
CCC/PLL Specification referring the reader to SmartGen was revised to refer instead to
the online help associated with the core (SAR 42564).
Additionally, note regarding SSOs was added.
2-113,
2-114
Live at Power-Up (LAPU) has been replaced with ’Instant On’.
NA
Revision 22
The "Security" section was modified to clarify that Microsemi does not support read- 1-2
(September 2012) back of programmed data.
Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip N/A
(SoC) throughout the document (SAR 40271).
Revision 21
(May 2012)
Under AGL125, in the Package Pin list, CS121 was incorrectly added to the datasheet I to IV
in revision 19 and has been removed (SAR 38217).
Corrected the inadvertent error for Max Values for LVPECL VIH and revised the same
to ’3.6’ in Table 2-151 · Minimum and Maximum DC Input and Output Levels (SAR
37685).
2-82
Figure 2-38 • FIFO Read and Figure 2-39 • FIFO Write have been added (SAR 34841). 2-125
The following sentence was removed from the VMVx description in the "Pin 3-1
Descriptions" section: "Within the package, the VMV plane is decoupled from the
simultaneous switching noise originating from the output buffer VCCI domain" and
replaced with “Within the package, the VMV plane biases the input stage of the I/Os in
the I/O banks” (SAR 38317). The datasheet mentions that "VMV pins must be
connected to the corresponding VCCI pins" for an ESD enhancement.
Pin description table for AGL125 CS121 was removed as it was incorrectly added to the -
datasheet in revision 19 (SAR 38217).
Revision 20
(March 2012)
Notes indicating that AGL015 is not recommended for new designs have been added. I to IV
The "Devices Not Recommended For New Designs" section is new (SAR 35015).
Notes indicating that device/package support is TBD for AGL250-QN132 and I to IV
AGL060-FG144 have been reinserted (SAR 33689).
Values for the power data for PAC1, PAC2, PAC3, PAC4, PAC7, and PAC8 were
revised in Table 2-19 • Different Components Contributing to Dynamic Power
Consumption in IGLOO Devices and Table 2-21 • Different Components Contributing to
Dynamic Power Consumption in IGLOO Devices to match the SmartPower tool in
Libero software version 9.0 SP1 and Power Calculator spreadsheet v7a released on
08/10/2010 (SAR 33768).
2-13,
2-15
The reference to guidelines for global spines and VersaTile rows, given in the "Global
Clock Contribution—PCLOCK" section, was corrected to the "Spine Architecture"
section of the Global Resources chapter in the IGLOO FPGA Fabric User’s Guide
(SAR 34730).
2-17
Revision 23
5-1
Share Link: 