AGL400V5-VQG144I Просмотр технического описания (PDF) - Microsemi Corporation
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AGL400V5-VQG144I Datasheet PDF : 250 Pages
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Datasheet Information
Revision / Version
Revision 8 (cont’d)
Revision 7 (Jun 2008)
Packaging v1.5
Revision 6 (Jun 2008)
Packaging v1.4
Revision 5 (Mar 2008)
Packaging v1.3
Revision 4 (Mar 2008)
Product Brief v1.0
Changes
Page
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software
Settings, Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O
Software Settings, Table 2-15 • Summary of I/O Input Buffer Power (per pin) –
Default I/O Software Settings, and Table 2-16 • Summary of I/O Output Buffer
Power (per pin) – Default I/O Software Settings1 were updated to change PDC2
to PDC6 and PDC3 to PDC7. The table notes were updated to reflect that power
was measured on VCCI.
2-10
through
2-11
In Table 2-19 • Different Components Contributing to Dynamic Power
Consumption in IGLOO Devices, the description for PAC13 was changed from
Static to Dynamic.
2-13
Table 2-20 • Different Components Contributing to the Static Power Consumption
in IGLOO Devices and Table 2-22 • Different Components Contributing to the
Static Power Consumption in IGLOO Device were updated to add PDC6 and
PDC7, and to change the definition for PDC5 to bank quiescent power. Subtitles
were added to indicate type of devices and core supply voltage.
2-14,
2-16
The "Total Static Power Consumption—PSTAT" section was updated to revise the
calculation of PSTAT, including PDC6 and PDC7.
Footnote † was updated to include information about PAC13. The PLL
Contribution equation was changed from: PPLL = PAC13 + PAC14 * FCLKOUT to
PPLL = PDC4 + PAC13 * FCLKOUT.
The "QN132" package diagram was updated to include D1 to D4. In addition, note
1 was changed from top view to bottom view, and note 2 is new.
2-17
2-18
4-28
This document was divided into two sections and given a version number, starting
at v1.0. The first section of the document includes features, benefits, ordering
information, and temperature and speed grade offerings. The second section is a
device family overview.
Pin numbers were added to the "QN68" package diagram. Note 2 was added
below the diagram.
The "CS196" package and pin table was added for AGL250.
N/A
4-25
4-12
The "Low Power" section was updated to change "1.2 V and 1.5 V Core Voltage"
to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 12 µW)" was removed
from "Low Power Active FPGA Operation."
1.2_V was added to the list of core and I/O voltages in the "Advanced I/O" and
"I/Os with Advanced I/O Standards" section sections.
The "Embedded Memory" section was updated to remove the footnote reference
from the section heading and place it instead after "4,608-Bit" and "True Dual-Port
SRAM (except ×18)."
I
I, 1-7
I
5-8
Revision 23
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