AGL250V2-FG144Y Просмотр технического описания (PDF) - Microsemi Corporation

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AGL250V2-FG144Y

IGLOO Low Power Flash FPGAs with Flash* Freeze Technology

Microsemi Corporation 

IGLOO Low Power Flash FPGAs

Power Consumption of Various Internal Resources

Table 2-19 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices

For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage

Device Specific Dynamic Power

(µW/MHz)

Parameter

Definition

AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015

PAC1

Clock contribution of a

Global Rib

7.778 6.221 6.082 4.460 4.446 2.736 0.000 0.000

PAC2

Clock contribution of a

Global Spine

4.334 3.512 2.759 2.718 1.753 1.971 3.483 3.483

PAC3

Clock contribution of a

VersaTile row

1.379 1.445 1.377 1.483 1.467 1.503 1.472 1.472

PAC4

Clock contribution of a

VersaTile used as a

sequential module

0.151 0.149 0.151 0.149 0.149 0.151 0.146 0.146

PAC5

First contribution of a

VersaTile used as a

sequential module

0.057

PAC6

Second contribution of a

VersaTile used as a

sequential module

0.207

PAC7

Contribution of a

VersaTile used as a

combinatorial module

0.276 0.262 0.279 0.277 0.280 0.300 0.281 0.273

PAC8

Average contribution of a 1.161

routing net

1.147

1.193 1.273

1.076

1.088

1.134 1.153

PAC9

Contribution of an I/O

input pin (standard-

dependent)

See Table 2-13 on page 2-10 through Table 2-15 on page 2-11.

PAC10

Contribution of an I/O

output pin (standard-

dependent)

See Table 2-16 on page 2-11 through Table 2-18 on page 2-12.

PAC11

Average contribution of a

RAM block during a read

operation

25.00

PAC12

Average contribution of a

RAM block during a write

operation

30.00

PAC13

Dynamic PLL

2.70

contribution

Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

spreadsheet calculator or SmartPower tool in Libero SoC.

Revision 23

2- 13

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