AGL250V2-FG144Y Просмотр технического описания (PDF) - Microsemi Corporation

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AGL250V2-FG144Y

IGLOO Low Power Flash FPGAs with Flash* Freeze Technology

Microsemi Corporation 

IGLOO Low Power Flash FPGAs

Table 2-21 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices

For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage

Device Specific Dynamic Power

(µW/MHz)

Parameter

Definition

AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015

PAC1

Clock contribution of a

Global Rib

4.978 3.982 3.892 2.854 2.845 1.751 0.000 0.000

PAC2

Clock contribution of a

Global Spine

2.773 2.248 1.765 1.740 1.122 1.261 2.229 2.229

PAC3

Clock contribution of a

VersaTile row

0.883 0.924 0.881 0.949 0.939 0.962 0.942 0.942

PAC4

Clock contribution of a

VersaTile used as a

sequential module

0.096 0.095 0.096 0.095 0.095 0.096 0.094 0.094

PAC5

First contribution of a

VersaTile used as a

sequential module

0.045

PAC6

Second contribution of a

VersaTile used as a

sequential module

0.186

PAC7

Contribution of a

VersaTile used as a

combinatorial module

0.158 0.149 0.158 0.157 0.160 0.170 0.160 0.155

PAC8

Average contribution of a 0.756

routing net

0.729

0.753

0.817

0.678 0.692

0.738

0.721

PAC9

Contribution of an I/O

input pin (standard-

dependent)

See Table 2-13 on page 2-10 through Table 2-15 on page 2-11.

PAC10

Contribution of an I/O

output pin (standard-

dependent)

See Table 2-16 on page 2-11 through Table 2-18 on page 2-12.

PAC11

Average contribution of a

RAM block during a read

operation

25.00

PAC12

Average contribution of a

RAM block during a write

operation

30.00

PAC13

Dynamic PLL contribution

2.10

Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

spreadsheet calculator or SmartPower tool in Libero SoC.

Revision 23

2- 15

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