MP7529A Просмотр технического описания (PDF) - Exar Corporation
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MP7529A Datasheet PDF : 12 Pages
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MP7529A
DIGITAL INTERFACE
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 10nA.
The control input DAC A/DAC B selects which DAC can ac-
cept data from the input port. Inputs CS and WR control the op-
erating mode of the selected DAC (Table 1.). When CS and WR
are both low the selected DAC is in the write mode. The input
data latches of the selected DAC are transparent and its analog
output responds to activity on DB0-DB7 (Write mode). The se-
lected DAC latch retains the data which was present on
DB0-DB7 just prior to CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches (Hold mode).
tCS
tCH
CS
DAC A/
DAC B
WR
DB7-DB0
tAS
tAH
VALID
tWR
tDS
tDH
VALID
DAC A/
DAC B
CS
WR DAC A
L
H
X
X
L = Low State
L
L
L
L
H
X
X
H
H = High State
WRITE
HOLD
HOLD
HOLD
X = Don’t Care
DAC B
HOLD
WRITE
HOLD
HOLD
NOTE:
1. Timing measured from (VIH + VIL) /2
Figure 1. Write Cycle Timing Diagram
Table 1. DACs Mode Selection
MICROPROCESSOR INTERFACE
A0-A15
VMA
CPU
6800 φ2
ADDRESS
DECODE
LOGIC
A**
A+1***
D0–D7
ADDRESS BUS
DAC A/DAC B
CS DAC A
WR MP7529A*
DB0 DAC B
DB7
DATA BUS
*Analog circuitry has been omitted for clarity
**A = Decoded 7529A DAC A Address
***A+1 = Decoded 7529A DAC B Address
Figure 2. MP7529A Dual DAC to 6800
CPU Interface
NOTE:
8085 instruction shld (store H & L direct) can update
both DACS with data from H and L registers
A8-A15
CPU
8085
WR
ALE
AD0–AD7
ADDRESS
DECODE
LOGIC
A**
A+1***
LATCH
8212
ADDRESS BUS
DAC A/DAC B
CS DAC A
WR MP7529A*
DB0 DAC B
DB7
ADDR/DATA BUS
*Analog circuitry has been omitted for clarity
**A = Decoded 7529A DAC A Address
***A+1 = Decoded 7529A DAC B Address
Figure 3. MP7529A Dual DAC to 8085
CPU Interface
Rev. 2.00
5
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