Dual-Phase, Quick-PWM Controller
for IMVP6+ CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS =
VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57kΩ from FB to VPS, [D6–D0] = [0101000]; TA = -40°C to
+105°C, unless otherwise noted.)
PARAMETER
GATE DRIVERS
DH_ Gate-Driver On-Resistance
DL_ Gate-Driver On-Resistance
Internal BST_ Switch
On-Resistance
LOGIC AND I/O
Logic Input High Voltage
Logic Input Low Voltage
Low-Voltage Logic Input
High Voltage
SYMBOL
CONDITIONS
RON(DH_)
RON(DL_)
BST_ - LX_ forced
to 5V
High state (pullup)
Low state (pulldown)
High state (pullup)
Low state (pulldown)
RON(BST_) IBST_ = 10mA
VIH
VIL
VIHLV
SHDN, PGDIN, DPRSLPVR
SHDN, PGDIN, DPRSLPVR
PSI, D0–D6, DPRSTP
MIN
2.3
0.67
TYP
MAX UNITS
2.5
2.0
2.0
0.7
20
V
1.0
V
V
Low-Voltage Logic Input
Low Voltage
VILLV PSI, D0–D6, DPRSTP
0.33
V
Note 2: DC output accuracy specifications refer to the trip level of the error amplifier. The output voltage has a DC regulation higher
than the trip level by 50% of the output ripple. When pulse skipping, the output rises by approximately 1.5% when transition-
ing from continuous conduction to no load.
Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DL_ and DH_ pins, with LX_ forced to
GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-
circuit times might be different due to MOSFET switching speeds.s
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