MAX5093 Просмотр технического описания (PDF) - Maxim Integrated

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MAX5093

4V to 72V Input LDOs with Boost Preregulator

Maxim Integrated 

MAX5092/MAX5093

4V to 72V Input LDOs with Boost Preregulator

Internal Regulator (VL)

An internal regulator (VL) is used to supply all internal low-

voltage blocks. Bypass VL to SGND with a 1μF ceramic

capacitor placed as close to the IC as possible. VVL regu-

lates to 5.5V when VBSOUT is above 5.5V. VVL tracks the

voltage at BSOUT when VBSOUT is below 5.5V.

Power-On-Reset Output (RESET)

The MAX5092_/MAX5093_ contain an open-drain output

(RESET) that indicates when the LDO output (VOUT) is out

of regulation. If the output of the LDO falls below 90% of the

nominal output voltage, RESET pulls low after a short delay.

Once the output rises above 92% of the nominal output volt-

age, RESET goes high impedance after the programmed

reset timeout period. Connect a 100kΩ pullup resistor from

OUT to RESET. See the CT Capacitor Selection section for

details on setting the RESET timeout period.

Enable and Hold Inputs

The MAX5092_/MAX5093_ utilize two logic inputs, EN

(active-high) and HOLD (active low), to implement a self-

holding circuit with no additional components. For exam-

ple, an ignition switch drives EN high and the regulator

turns on. If HOLD is then driven low, the regulator remains

on even if EN goes low. As long as HOLD is forced low

and remains low after initial regulator power-up, the

regulator remains on. From this state, release HOLD

(an internal current source connects HOLD to OUT), or

connect HOLD to OUT to turn the regulator off. Drive EN

low and HOLD high to place the IC into shutdown mode.

Shutdown mode reduces supply current to 5μA. Figure 3

shows the timing diagram for the enable and hold func-

tions. Table 1 shows the state of the regulator output

with respect to the voltage level at EN and HOLD with

reference to Figure 3. Connect HOLD to OUT or leave

unconnected to disable the hold feature and use EN as a

standard on/off control input.

HOLD

EN

OUT

ORDER 1

2

3

4

56

Figure 3. Enable and Hold Timing Diagram

Table 1. Truth Table for Enable and Hold Timing Diagram

ORDER

1

2

3

4

5

5

EN

Low

High

Low

High

Low

High

HOLD

X

Released

Released

Low

Released

X

OUT

Off

On

Off

On

Off

On

COMMENTS

Initial State. EN has a 500nA pulldown to GND. HOLD has an internal current source to OUT.

HOLD follows OUT.

Regulator output is active when EN is pulled high. HOLD is in release state, and it follows

OUT.

HOLD is in release state. OUT follows EN.

HOLD is pulled low externally after OUT turns on. The regulator output is forced on

regardless of the state of EN. A self-holding state.

HOLD is released after EN is pulled low. Output turns off.

Regulator enabled. Normal turn-on behavior. Regulator follows EN and HOLD follows OUT.

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