MAX8751ETJ Просмотр технического описания (PDF) - Maxim Integrated

Номер в каталоге

Компоненты Описание

производитель

MAX8751ETJ

Fixed-Frequency, Full-Bridge CCFL Inverter Controller

Maxim Integrated 

Fixed-Frequency, Full-Bridge CCFL

Inverter Controller

Pin Description (continued)

PIN

NAME

DESCRIPTION

18

GH2

Gate-Driver Output for High-Side MOSFET NH2

Gate-Driver Return for GH2. LX2 is the input to the primary current-limit and zero-crossing

19

LX2

comparators. The controller senses the voltage across the low-side MOSFET NL2 (LX2 - GND) for

primary overcurrent condition and zero-crossing detection.

20

IN

Supply Input. Input to the internal 5.3V linear regulator that powers the device. Bypass IN to GND with

a 0.1µF ceramic capacitor.

21

VCC

5.3V/20mA Linear Regulator Output. Supply voltage for the device including the low-side gate drivers

GL1 and GL2. Bypass VCC with a 1.0µF ceramic capacitor to GND.

Gate Driver Return for GH1. LX1 is the input to the primary current-limit and zero-crossing

22

LX1

comparators. The controller senses the voltage across the low-side MOSFET NL1 (LX1 - GND) for

primary overcurrent condition and zero-crossing detection.

23

GH1

Gate Driver Output for High-Side MOSFET NH1

24

BST1

High-Side Gate-Driver GH1 Supply Input. The MAX8751 includes an integrated boost diode. Connect

a 0.1µF capacitor between LX1 and BST1 to complete the bootstrap circuit.

25

GL1

Gate-Driver Output for Low-Side MOSFET NL1

26

PGND1 Power Ground. PGND is the return for the GL1 gate driver.

27

GND

System Ground

28

PCOMP

Compensation Node of the Phase-Lock Loop. Connect a 0.1µF capacitor between PCOMP and GND

to compensate the PLL.

Transconductance Error-Amplifier Output. A compensation capacitor of 0.01µF connected between

29

COMP COMP and GND stabilizes the controller. The rise and fall time of the lamp-current envelope in DPWM

operation is also determined by the COMP capacitor.

Lamp Current-Feedback Input. The IFB sense signal is internally full-wave rectified. The average

30

IFB

value of the rectified signal is regulated to 790mV (typ) by controlling the on-time of the high-side

MOSFET. An open-lamp fault is generated if the IFB is continuously below 790mV (typ) for a period

set by TFLT. See the Lamp-Out Protection and Setting the Fault-Delay Time sections for details.

31

PS2

Phase-Shift Select Input for Slave. For details, see the Slave Operation (HFCK, LFCK, PSCK, DPWM)

section.

Transformer Secondary Current-Feedback Input. When the average voltage on ISEC exceeds the

32

ISEC

internal overcurrent threshold, the controller turns on an internal current sink, discharging the COMP

capacitor. An RC current-sense network connected between the low-voltage end of the transformer

secondary and the ground allows setting the maximum secondary current during short-circuit fault.

—

PAD

Exposed Backside Pad. Connect PAD to GND.

______________________________________________________________________________________ 11

Share Link: