MAX9526ATJ/V(2010) Просмотр технического описания (PDF) - Maxim Integrated
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MAX9526ATJ/V Datasheet PDF : 38 Pages
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Low-Power, High-Performance
NTSC/PAL Video Decoder
Interrupt Mask Register 0
REG
0x02
B7
IVID1
B6
IVID2
B5
B4
B3
B2
B1
B0
0
ICTHR
IADCOVR
IHLOCK
INONSTD
ILSTLCK
Active Video 1 Interrupt (IVID1)
1 = Change in VID1 bit status triggers a hardware
interrupt.
0 = No interrupt on VID1 changes (default).
See register 0x00, B7.
Horizontal Lock Interrupt Enable (IHLOCK)
1 = Change in HLOCK bit from 1 to 0 triggers a
hardware interrupt.
0 = No interrupt on HLOCK changes (default).
See register 0x00, B2.
Active Video 2 Interrupt (IVID2)
1 = Change in VID2 bit status triggers a hardware
interrupt.
0 = No interrupt on VID2 changes (default).
See register 0x00, B6.
Nonstandard Video Interrupt Enable (INONSTD)
1 = Change in NONSTD bit from 0 to 1 triggers a
hardware interrupt.
0 = No interrupt on NONSTD changes (default).
See register 0x00, B1.
Color Kill Threshold Interrupt (ICTHR)
1 = Transition in CTHR bit from 0 to 1 triggers a hard-
ware interrupt.
0 = No interrupt on CTHR changes (default).
See register 0x00, B4.
Demodulator Lock Interrupt Enable (ILSTLCK)
1 = Change in LSTLCK bit from 0 to 1 triggers a
hardware interrupt.
0 = No interrupt on LSTLCK changes (default).
See register 0x00, B0.
ADC Out-of-Range Interrupt Enable (IADCOVR)
1 = Change in ADCOVR bit from 0 to 1 triggers a
hardware interrupt.
0 = No interrupt on ADCOVR changes (default).
See register 0x00, B3.
Interrupt Mask Register 1
REG
B7
B6
B5
B4
B3
B2
B1
B0
0x03
0
IL525
0
0
0
0
0
IACP
525 Line Video Interrupt Enable (IL525)
1 = Change in L525 bit status triggers a hardware
interrupt.
0 = No interrupt on L525 changes (default).
This interrupt is masked by the HLOCK and LSTLCK
status. Changes in the L525 status triggers a hardware
interrupt only when HLOCK = 1 and LSTLCK = 0. See
register 0x01, B6.
Analog Copy Protection Interrupt Enable (IACP)
1 = Any change in ACP status bit (register 0x01, B0)
triggers a hardware interrupt.
0 = No interrupt on analog copy protection changes
(default).
See register 0x01, B0.
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