UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
(A)
DI
Control Voltage
Inductor
Current
m1
m2
Dl
)
Dl
m2
m1
Oscillator Period
Dl
)
Dl
m2
m1
m2
m1
t0
t1
t2
Control Voltage
(B)
m3
DI
m1
m2
Oscillator Period
t4
t5
t3
Inductor
Current
t6
Figure 20. Continuous Current Waveforms
Vref
8(14)
RT
R
Bias
R
External
Sync
Input
CT
4(7)
0.01
47
2(3)
Osc
+
2R
EA
R
1(1)
5(9)
The diode clamp is required if the Sync amplitude is large enough to cause the bottom
side of CT to go more than 300 mV below ground.
Figure 21. External Clock Synchronization
VCC
Vin
7(12)
RA
8
RB
5.0k
6
5
5.0k
2
C
5.0k
1
4
R
Q
S
MC1455
8(14)
3
4(7)
7
2(3)
1(1)
R
Bias
R
Osc
+
2R
EA
R
5.0V Ref
8(14)
R
+
Bias
−
4(7)
R2
2(3)
R
Osc
+
1.0 mA
+
−
VClamp
EA
2R
R
1.0V
S
Q
R
Comp/Latch
7(11)
Q1
6(10)
5(8)
1(1)
R1
5(9)
3(5)
RS
f
+
(RA
1.44
) 2RB)C
D(max)
+
RA
RB
) 2RB
To Additional
UCX84XBs
5(9)
VClamp ≈
1.67
ǒ Ǔ R2
R1
)
1
ǒ Ǔ + 0.33x10−3
R1R2
R1 ) R2
Where: 0 ≤ VClamp ≤ 1.0 V
Ipk(max)
[
VClamp
RS
Figure 22. External Duty Cycle Clamp and
Multi−Unit Synchronization
Figure 23. Adjustable Reduction of Clamp Level
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