WM9701A Просмотр технического описания (PDF) - Wolfson Microelectronics plc
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WM9701A Datasheet PDF : 24 Pages
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WM9701A
Production Data
GENERAL PURPOSE REGISTER (INDEX 20h)
This register is used to control several miscellaneous functions of the WM9701A.
Below is a summary of each bit and its function. Only the MIX, MS and LPBK bits are supported by
WM9701A. The MS bit controls the Mic selector. The LPBK bit enables loop back of the ADC output
to the DAC input without involving the AC-link, allowing for full system performance measurements.
The function default value is 0000h which is all off.
BIT
FUNCTION
POP
ST
3D
LD
LLBK
RLBK
MIX
MS
LPBK
PCM out path and mute, 0 = pre 3D, 1 = post 3D
Simulated stereo enhancement, on/off 1 = on
3D stereo enhancement on/off, 1 = on
Loudness (bass boost) on/off, 1 = on
Local loop back - for modem, line Codec
Remote loop back - for modem, line Codec
Mono output select 0 = Mix, 1 = Mic
Mic select 0 = Mic1, 1 = Mic2
ADC/DAC/ loop back mode
Table 7 General Purpose Register Function
WM9701A
SUPPORT
No
No
No
No
No
No
Yes
Yes
Yes
3D CONTROL REGISTER (INDEX 22h)
This optional register is used to control the centre and/or depth of the 3D stereo enhancement
function built into of the AC’97 component. This feature is not supported by the WM9701A.
MODEM SAMPLE RATE REGISTER (INDEX 24h)
This register controls what sample rate AC’97 is sending or receiving samples for the optional
Modem in and out. This feature is not supported by WM9701A.
POWER DOWN CONTROL/STATUS REGISTER (INDEX 26h)
This read/write register is used to program power down states and monitor subsystem readiness.
The lower half of this register is read only status, a 1 indicating that the subsection is “ready”. Ready
is defined as the subsection able to perform in its nominal state. When this register is written to the
bit values that come in on AC-link will have no effect on read only bits 0 to 7.
When the AC-link “Codec Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1 it indicates that the
AC-link and WM9701A control and status registers are in a fully operational state. The AC’97
controller must further probe this power down Control/Status Register to determine exactly which
subsections, if any, are ready.
READ BIT
MDM
REF
ANL
DAC
ADC
FUNCTION
Modem section ready – not supported
VREFs up to nominal level
Analogue mixers, etc ready
DAC section ready to accept data
ADC section ready to transmit data
Table 8 Power Down Status Register Function
The power down modes are as follows. The first three bits are to be used individually rather than in
combination with each other. The last bit PR3 can be used in combination with PR2 or by itself. PR0
and PR1 control the PCM ADCs and DACs only. PR7 independently controls the optional modem
ADC and DAC, not supported by WM9701A.
WOLFSON MICROELECTRONICS LTD.
PD Rev 3.2 January 2001
18
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