QHX220ICT7 Просмотр технического описания (PDF) - Intersil

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производитель

QHX220ICT7

Active Isolation Enhancer and Interference Canceller

Intersil 

QHx220

SPI Bus Characteristics

CLK

TC2BEB

TCP

TBEB2C

TCL

TCH

BUSENBAR

24BIT

DATA

MSB

LSB

TDH

TDS

Data register lock

FIGURE 2. SPI BUS TIMING DIAGRAM

SPI BUS TIMING REQUIREMENT

SYMBOL

PARAMETER

tCP

tCL

tCH

tBEB2C

tC2BEB

tDS

tDH

SPI clock period

Clock pulse width low

Clock pulse width high

BUSENBAR Fall to CLK Rise Setup Time

CLK Rise BUSENBAR Fall Delay

Data Setup Time

Data Hold Time

MIN

100ns

40ns

40ns

5ns

40ns

20ns

0ns

10BIT I-DAC

<23:14>

TABLE 1. SPI BUS DATA FORMAT

10BIT Q-DAC

<13:4>

FREQ RANGE

<3:2>

GAIN

<1>

TYP

MAX

SPARE

<0>

5

FN6986.0

October 20, 2009

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