UPD703101AGJ-33-XX-UEN Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD703101AGJ-33-XX-UEN

V850E/MS1™ 32/16-BIT SINGLE-CHIP MICROCONTROLLERS

NEC => Renesas Technology 

µPD703100A-33, 703100A-40, 703101A-33, 703102A-33

Pin Name

I/O

Function

LCAS

O

Column address strobe signal output for DRAM’s lower data

UCAS

O

Column address strobe signal output for DRAM’s higher data

RAS0 to RAS3

O

Low address strobe signal output for DRAM

RAS4

RAS5

RAS6

RAS7

BCYST

O

Strobe signal output indicating start of bus cycle

CS0 to CS3

O

Chip select signal output

CS4

CS5

CS6

CS7

WAIT

REFRQ

IOWR

IORD

DMARQ0 to

DMARQ3

DMAAK0 to

DMAAK3

TC0 to TC3

I

Control signal input for inserting waits in bus cycle

O

Refresh request signal output for DRAM

O

DMA write strobe signal output

O

DMA read strobe signal output

I

DMA request signal input

O

DMA acknowledge signal output

O

DMA end (terminal count) signal output

HLDAK

HLDRQ

ANI0 to ANI7

NMI

CLKOUT

CKSEL

MODE0 to

MODE3

RESET

X1

X2

ADTRG

AVREF

AVDD

AVSS

O

Bus hold acknowledge output

I

Bus hold request input

I

Analog input to A/D converter

I

Non-maskable interrupt request input

O

System clock output

I

Input for specifying clock generator’s operation mode

I

Specify operation modes

I

System reset input

I

Oscillator connection for system clock. Input is via X1 when using an

—

external clock.

I

A/D converter external trigger input

I

Reference voltage input for A/D converter

—

Positive power supply for A/D converter

—

Ground potential for A/D converter

(3/4)

Alternate Function

P90/LWR

P91/UWR

P80/CS0 to P83/CS3

P84/CS4/IOWR

P85/CS5/IORD

P86/CS6

P87/CS7

P94

P80/RAS0 to

P83/RAS3

P84/RAS4/IOWR

P85/RAS5/IORD

P86/RAS6

P87/RAS7

PX6

PX5

P84/RAS4/CS4

P85/RAS5/CS5

P04/INTP100 to

P07/INTP103

P14/INTP110 to

P17/INTP113

P104/INTP120 to

P107/INTP123

P96

P97

P70 to P77

P20

PX7

—

—

—

—

—

P127/INTP153

—

—

—

16

Preliminary Data Sheet U14168EJ2V0DS00

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